haroonrl / DNN_HLS_AcceleratorLinks
This repository contains source code for CNN layers of ALexNet using Xilinx HLS Vivado.
☆10Updated 3 years ago
Alternatives and similar repositories for DNN_HLS_Accelerator
Users that are interested in DNN_HLS_Accelerator are comparing it to the libraries listed below
Sorting:
- A CNN accelerator design inspired by MIT Eyeriss project☆20Updated 4 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 4 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆14Updated 6 years ago
- A collection of tutorials for the fpgaConvNet framework.☆48Updated last year
- Verilog implementation of Softmax function☆80Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆65Updated 3 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- ☆124Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆180Updated 6 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆97Updated 4 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Updated 2 years ago
- ☆10Updated last year
- An FPGA Accelerator for Transformer Inference☆93Updated 3 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- RTL code for the DPU chip designed for irregular graphs☆13Updated 3 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- 2020 xilinx summer school☆19Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆43Updated 2 years ago
- ☆32Updated 10 months ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 4 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆133Updated 6 months ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆124Updated last year
- Library of approximate arithmetic circuits☆62Updated 3 weeks ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆13Updated last year
- ☆11Updated last year