haroonrl / DNN_HLS_AcceleratorLinks
This repository contains source code for CNN layers of ALexNet using Xilinx HLS Vivado.
☆9Updated 3 years ago
Alternatives and similar repositories for DNN_HLS_Accelerator
Users that are interested in DNN_HLS_Accelerator are comparing it to the libraries listed below
Sorting:
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 3 years ago
- ☆10Updated 8 months ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- 2020 xilinx summer school☆17Updated 4 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated 2 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆13Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- ☆28Updated 4 months ago
- cnn accelerator in vivado HLS☆8Updated 4 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆15Updated 4 years ago
- A collection of tutorials for the fpgaConvNet framework.☆43Updated 10 months ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- Open-source of MSD framework☆16Updated last year
- ☆11Updated last year
- Hardware accelerator for convolutional neural networks☆47Updated 2 years ago
- A DAG processor and compiler for a tree-based spatial datapath.☆13Updated 2 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 6 years ago
- ☆26Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 4 years ago
- ☆21Updated 2 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 3 years ago
- ☆113Updated 5 years ago
- ☆17Updated 2 years ago
- IC implementation of TPU☆128Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆93Updated 2 weeks ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆164Updated 5 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago