ehw-fit / ariths-gen
Generator of arithmetic circuits (multipliers, adders) and approximate circuits
☆33Updated 3 months ago
Alternatives and similar repositories for ariths-gen
Users that are interested in ariths-gen are comparing it to the libraries listed below
Sorting:
- Benchmarks for Approximate Circuit Synthesis☆16Updated 4 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆83Updated last year
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆30Updated last year
- ☆59Updated 2 weeks ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆41Updated 7 months ago
- This is a python repo for flattening Verilog☆16Updated this week
- ☆27Updated 5 years ago
- ☆25Updated last year
- SRAM☆22Updated 4 years ago
- DASS HLS Compiler☆29Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆48Updated 8 months ago
- Collection of digital hardware modules & projects (benchmarks)☆58Updated last week
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆27Updated 5 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 2 months ago
- Dataset for ML-guided Accelerator Design☆36Updated 5 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆54Updated 3 years ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 3 years ago
- ☆16Updated 4 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- sram/rram/mram.. compiler☆34Updated last year
- ☆15Updated 2 years ago
- ☆18Updated 10 months ago
- Supplemental technology files for ASAP7 PDK with Synopsys design flow☆13Updated 2 years ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆27Updated last year
- ☆22Updated 10 months ago
- ABACUS is a tool for approximate logic synthesis☆14Updated 4 years ago
- ☆27Updated 7 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- The Verilog source code for DRUM approximate multiplier.☆30Updated 2 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆43Updated 10 months ago