RaulMurillo / Flo-PositLinks
Posit Arithmetic Cores generated with FloPoCo
☆25Updated last year
Alternatives and similar repositories for Flo-Posit
Users that are interested in Flo-Posit are comparing it to the libraries listed below
Sorting:
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- DASS HLS Compiler☆29Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Universal number Posit HDL Arithmetic Architecture generator☆63Updated 6 years ago
- ☆87Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- PACoGen: Posit Arithmetic Core Generator☆75Updated 6 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Next generation CGRA generator☆113Updated this week
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆26Updated 6 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 2 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- FPGA version of Rodinia in HLS C/C++☆38Updated 4 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆31Updated 11 months ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 3 months ago
- ☆60Updated this week
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- Public release☆57Updated 5 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆86Updated 3 months ago
- Project repo for the POSH on-chip network generator☆50Updated 5 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆39Updated last week
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 6 months ago
- ☆30Updated 6 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆46Updated 9 months ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆57Updated 10 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆68Updated 5 months ago
- ☆58Updated 5 years ago
- ☆63Updated 4 months ago