RaulMurillo / Flo-PositLinks
Posit Arithmetic Cores generated with FloPoCo
☆24Updated last year
Alternatives and similar repositories for Flo-Posit
Users that are interested in Flo-Posit are comparing it to the libraries listed below
Sorting:
- An Open-Hardware CGRA for accelerated computation on the edge.☆28Updated 9 months ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆11Updated 7 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Universal number Posit HDL Arithmetic Architecture generator☆60Updated 6 years ago
- DASS HLS Compiler☆29Updated last year
- PACoGen: Posit Arithmetic Core Generator☆72Updated 5 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆46Updated 8 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆37Updated 3 weeks ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 3 weeks ago
- ☆86Updated last year
- ☆29Updated 6 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated this week
- ☆19Updated 7 years ago
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- ☆60Updated last month
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆26Updated 5 years ago
- ☆11Updated last month
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆63Updated 5 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆41Updated 2 years ago
- A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating…☆23Updated 2 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆35Updated 4 months ago
- An open source, parameterized SystemVerilog digital hardware IP library☆27Updated last year
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆41Updated last month
- CGRA framework with vectorization support.☆32Updated last week