RaulMurillo / Flo-Posit
Posit Arithmetic Cores generated with FloPoCo
☆24Updated 6 months ago
Alternatives and similar repositories for Flo-Posit:
Users that are interested in Flo-Posit are comparing it to the libraries listed below
- Universal number Posit HDL Arithmetic Architecture generator☆53Updated 5 years ago
- A tool to generate optimized hardware files for univariate functions.☆25Updated 9 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- HLS for Networks-on-Chip☆32Updated 3 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆50Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating…☆21Updated 2 years ago
- sram/rram/mram.. compiler☆30Updated last year
- ☆39Updated 4 months ago
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- ☆52Updated 11 months ago
- ☆86Updated 10 months ago
- Library of approximate arithmetic circuits☆53Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆29Updated last year
- Next generation CGRA generator☆108Updated this week
- ☆27Updated 5 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆30Updated this week
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- Project repo for the POSH on-chip network generator☆43Updated last year
- Open source process design kit for 28nm open process☆46Updated 8 months ago
- ☆40Updated 5 years ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆32Updated this week
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆37Updated 4 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆26Updated 3 months ago
- AMC: Asynchronous Memory Compiler☆47Updated 4 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆75Updated 9 months ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆69Updated last month