RaulMurillo / Flo-Posit
Posit Arithmetic Cores generated with FloPoCo
☆23Updated 4 months ago
Related projects ⓘ
Alternatives and complementary repositories for Flo-Posit
- Universal number Posit HDL Arithmetic Architecture generator☆52Updated 5 years ago
- PACoGen: Posit Arithmetic Core Generator☆64Updated 5 years ago
- ☆86Updated 8 months ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆47Updated 4 years ago
- ☆55Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆155Updated this week
- Next generation CGRA generator☆106Updated this week
- ☆51Updated 9 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- ☆27Updated 5 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆113Updated this week
- An Open-Source Tool for CGRA Accelerators☆56Updated 2 months ago
- ☆38Updated last month
- HLS for Networks-on-Chip☆30Updated 3 years ago
- Systolic-array based Deep Learning Accelerator generator☆24Updated 3 years ago
- Library of approximate arithmetic circuits☆49Updated 2 years ago
- ☆82Updated 4 months ago
- A DSL for Systolic Arrays☆78Updated 5 years ago
- ☆69Updated last year
- SAMO: Streaming Architecture Mapping Optimisation☆32Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆46Updated 7 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆39Updated 5 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated this week
- FPGA version of Rodinia in HLS C/C++☆31Updated 3 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆94Updated last year
- A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating…☆20Updated 2 years ago