dimdano / adaptLinks
Fast Emulation of Approximate DNN Accelerators in PyTorch
☆29Updated last year
Alternatives and similar repositories for adapt
Users that are interested in adapt are comparing it to the libraries listed below
Sorting:
- ☆31Updated 9 months ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆95Updated 4 years ago
- ☆18Updated 2 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 3 years ago
- ☆42Updated last year
- ☆35Updated 5 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 5 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆43Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- ☆72Updated 2 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 4 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆74Updated 2 months ago
- ☆71Updated 5 years ago
- MICRO22 artifact evaluation for Sparseloop☆46Updated 3 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆54Updated 2 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆62Updated 2 months ago
- ☆35Updated 6 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- A collection of tutorials for the fpgaConvNet framework.☆47Updated last year
- ☆19Updated 7 months ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- A general framework for optimizing DNN dataflow on systolic array☆38Updated 5 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- Implementation of Microscaling data formats in SystemVerilog.☆28Updated 5 months ago
- HLS implemented systolic array structure☆41Updated 8 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 4 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 10 months ago
- ☆26Updated 3 years ago