manish-kj / Posit-HDL-Arithmetic

Related projects ⓘ

Alternatives and complementary repositories for Posit-HDL-Arithmetic

• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆64Updated 5 years ago
• Xilinx / logicnets
  ☆83Updated 5 months ago
• RaulMurillo / Flo-Posit
  Posit Arithmetic Cores generated with FloPoCo
  ☆23Updated 4 months ago
• icgrp / prflow_nested_dfx
  Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)
  ☆12Updated 8 months ago
• ehw-fit / evoapproxlib
  Library of approximate arithmetic circuits
  ☆51Updated 2 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆65Updated 3 months ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆47Updated 4 years ago
• isi-rcg / spicy
  Hot & Spicy tool suite
  ☆23Updated 2 years ago
• qleenju / PDPU
  PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
  ☆35Updated last year
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆39Updated 4 years ago
• UCLA-VAST / FlexCNN
  ☆70Updated last year
• kkiningh / cs231n-project
  CNN accelerator
  ☆26Updated 7 years ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 5 years ago
• lana555 / dynamatic
  ☆87Updated 8 months ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆63Updated 5 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆48Updated last year
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆31Updated 3 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆78Updated 5 years ago
• awai54st / LUTNet
  ☆55Updated 4 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆63Updated last year
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆24Updated 4 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆60Updated 5 years ago
• Zaoldyeckk / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆51Updated 6 years ago
• template-hls / template-hls-float
  ☆27Updated 5 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆28Updated last year
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆49Updated 4 years ago
• brianhill11 / FPGA-CNN
  This repo is for ECE44x (Fall2015-Spring2016)
  ☆19Updated 6 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆58Updated last month
• ARM-software / DeepFreeze
  ☆40Updated 4 years ago