manish-kj / Posit-HDL-ArithmeticLinks
Universal number Posit HDL Arithmetic Architecture generator
☆64Updated 6 years ago
Alternatives and similar repositories for Posit-HDL-Arithmetic
Users that are interested in Posit-HDL-Arithmetic are comparing it to the libraries listed below
Sorting:
- PACoGen: Posit Arithmetic Core Generator☆75Updated 6 years ago
- Posit Arithmetic Cores generated with FloPoCo☆26Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆96Updated this week
- Train and deploy LUT-based neural networks on FPGAs☆100Updated last year
- ☆87Updated last year
- Next generation CGRA generator☆115Updated this week
- A DSL for Systolic Arrays☆82Updated 6 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆91Updated 9 months ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- ☆63Updated 6 months ago
- Project repo for the POSH on-chip network generator☆51Updated 7 months ago
- ☆60Updated 5 years ago
- CNN accelerator☆27Updated 8 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- Chisel components for FPGA projects☆127Updated 2 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 8 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆63Updated last week
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- Floating point modules for CHISEL☆31Updated 10 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆202Updated 3 years ago
- Public release☆57Updated 6 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- ☆30Updated 6 years ago