Alternatives and similar repositories for AM-Lib

Users that are interested in AM-Lib are comparing it to the libraries listed below

• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆132Updated 4 months ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆166Updated 5 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• Linger0 / SRAM-Compute-In-Memory
  A collection of research papers on SRAM-based compute-in-memory architectures.
  ☆29Updated last year
• ac-optimus / Convolution-using-systolic-arrays
  ☆66Updated 6 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆116Updated 5 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆90Updated 6 months ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆104Updated 4 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆80Updated 2 years ago
• dldldlfma / super_small_toy_tpu
  ☆42Updated 4 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆68Updated 3 years ago
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆88Updated 3 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆131Updated 5 years ago
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆14Updated 5 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆54Updated 4 years ago
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆38Updated 2 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago
• ehw-fit / evoapproxlib
  Library of approximate arithmetic circuits
  ☆55Updated 3 years ago
• CRAFT-THU / XB-Sim
  A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration
  ☆35Updated 3 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆76Updated 7 years ago
• taoyilee / clacc
  Deep Learning Accelerator (Convolution Neural Networks)
  ☆193Updated 7 years ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆63Updated last month
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆105Updated last month
• kuladeepsaireddy / OpenNoc
  ☆35Updated 6 years ago
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆200Updated 5 years ago
• neurosim / DNN_NeuroSim_V1.4
  Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
  ☆73Updated 6 months ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆29Updated 4 years ago
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆87Updated 8 months ago
• BUAA-CI-LAB / Literatures-on-SRAM-based-CIM
  A reading list for SRAM-based Compute-In-Memory (CIM) research.
  ☆82Updated 3 months ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆25Updated 4 years ago