skycrapers / AM-LibLinks
☆25Updated last year
Alternatives and similar repositories for AM-Lib
Users that are interested in AM-Lib are comparing it to the libraries listed below
Sorting:
- A collection of research papers on SRAM-based compute-in-memory architectures.☆28Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆162Updated 5 years ago
- An FPGA Accelerator for Transformer Inference☆83Updated 3 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- ☆34Updated 6 years ago
- ☆65Updated 6 years ago
- Library of approximate arithmetic circuits☆55Updated 2 years ago
- ☆33Updated 9 months ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆78Updated 4 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆119Updated last month
- ☆17Updated last month
- ☆112Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆45Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- Verilog implementation of Softmax function☆67Updated 2 years ago
- a Computing In Memory emULATOR framework☆11Updated last year
- A collection of tutorials for the fpgaConvNet framework.☆41Updated 9 months ago
- An integrated CGRA design framework☆89Updated 3 months ago
- Open-source of MSD framework☆16Updated last year
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- ☆35Updated 3 months ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆46Updated 8 months ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆29Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆54Updated 3 months ago