Alternatives and similar repositories for log-arithmetic

Users that are interested in log-arithmetic are comparing it to the libraries listed below

• manish-kj / Posit-HDL-Arithmetic
  Universal number Posit HDL Arithmetic Architecture generator
  ☆64Updated 6 years ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆75Updated 6 years ago
• awai54st / LUTNet
  ☆60Updated 5 years ago
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆98Updated last year
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆86Updated 4 months ago
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• RaulMurillo / deep-pensieve
  A Deep Learning Framework for the Posit Number System
  ☆30Updated last year
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 5 years ago
• spcl / hls_tutorial_examples
  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
  ☆201Updated 3 years ago
• ucb-bar / onnxruntime-riscv
  Fork of upstream onnxruntime focused on supporting risc-v accelerators
  ☆87Updated 2 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆81Updated 6 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆59Updated 3 years ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆31Updated 10 years ago
• pulp-platform / pulp-nn
  ☆85Updated last year
• VeriGOOD-ML / public
  ☆63Updated 4 months ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆27Updated 4 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆69Updated 3 years ago
• arcade-lab / tia-infrastructure
  ☆19Updated 7 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆132Updated 5 years ago
• Xilinx / finn-base
  Open Source Compiler Framework using ONNX as Frontend and IR
  ☆33Updated 3 years ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆281Updated last week
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆34Updated last year
• lana555 / dynamatic
  ☆87Updated last year
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆31Updated 5 years ago
• MicrochipTech / fpga-hls-examples
  Open-Source HLS Examples for Microchip FPGAs
  ☆46Updated 2 months ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆48Updated 7 months ago
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆200Updated 5 years ago
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆160Updated 2 years ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆127Updated 2 years ago
• thesps / conifer
  Fast inference of Boosted Decision Trees in FPGAs
  ☆55Updated 2 weeks ago