Supplemental technology files for ASAP7 PDK with Synopsys design flow
☆23Jan 27, 2023Updated 3 years ago
Alternatives and similar repositories for asap7_snps
Users that are interested in asap7_snps are comparing it to the libraries listed below
Sorting:
- KLayout technology files for ASAP7 FinFET educational process☆25Feb 5, 2023Updated 3 years ago
- RTLMeter benchmark suite☆29Updated this week
- OpenROAD Agent. This repository contain the model to train and testing the model using EDA Corpus dataset.☆21Jul 24, 2025Updated 7 months ago
- Characterizer☆31Nov 19, 2025Updated 3 months ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆39Aug 15, 2025Updated 6 months ago
- A Verilog Synthesis Regression Test☆37Jan 19, 2026Updated last month
- Tool to fetch and parse data about Efabless MPW projects☆15Jan 10, 2023Updated 3 years ago
- Benchmarks for Yosys development☆24Feb 17, 2020Updated 6 years ago
- Code for the paper "LLM Meets Bounded Model Checking: Neuro-symbolic Loop Invariant Inference" at ASE 2024☆26Sep 3, 2024Updated last year
- A bit-serial CPU☆20Sep 29, 2019Updated 6 years ago
- This repository provides supplementary material for our paper HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifi…☆20May 8, 2024Updated last year
- ☆20Mar 1, 2021Updated 5 years ago
- CPOL=0, CPHA=0 SPI core for practicing formal verification with yosys☆21May 20, 2020Updated 5 years ago
- Contains reference architecture scripts for running the OpenPiton regression using auto-scaling SLURM cluster.☆24Feb 25, 2026Updated last week
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆19Jul 22, 2020Updated 5 years ago
- ☆18Sep 2, 2020Updated 5 years ago
- ☆19Dec 29, 2014Updated 11 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆59Jun 25, 2024Updated last year
- An advanced automated reasoning tool for memory consistency model specifications.☆25Dec 6, 2021Updated 4 years ago
- RTLCheck☆25Oct 9, 2018Updated 7 years ago
- ☆22Nov 12, 2020Updated 5 years ago
- ☆24Feb 11, 2021Updated 5 years ago
- ☆27Aug 2, 2021Updated 4 years ago
- libView is a GUI tool for library file cell information view and comparison.☆26Jul 24, 2023Updated 2 years ago
- ☆38Jul 6, 2025Updated 8 months ago
- A library and command-line tool for querying a Verilog netlist.☆29Jun 13, 2022Updated 3 years ago
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆37Apr 3, 2025Updated 11 months ago
- A design automation framework to engineer decision diagrams yourself☆25Mar 2, 2026Updated last week
- Gaussian noise generator Verilog IP core☆32May 22, 2023Updated 2 years ago
- Artifact, reproducibility, and testing utilites for gem5☆23Jul 1, 2021Updated 4 years ago
- A Fast Floating-Point Satisfiability Solver☆29Jul 26, 2025Updated 7 months ago
- A LEF/DEF Utility.☆34Aug 15, 2019Updated 6 years ago
- ☆41Mar 2, 2023Updated 3 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆14Dec 1, 2023Updated 2 years ago
- ☆14May 24, 2025Updated 9 months ago
- This is a Login application for Android using Parse server.☆10Nov 26, 2018Updated 7 years ago
- Linux kernel driver for the Exar xr21v141x "vizzini" UART☆10Jul 2, 2015Updated 10 years ago
- Verilog hardware abstraction library☆46Updated this week