Supplemental technology files for ASAP7 PDK with Synopsys design flow
☆25Jan 27, 2023Updated 3 years ago
Alternatives and similar repositories for asap7_snps
Users that are interested in asap7_snps are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- KLayout technology files for ASAP7 FinFET educational process☆25Feb 5, 2023Updated 3 years ago
- Characterizer☆37Nov 19, 2025Updated 6 months ago
- reference block design for the ASAP7nm library in Cadence Innovus☆64Jun 25, 2024Updated last year
- Benchmarks for Yosys development☆24Feb 17, 2020Updated 6 years ago
- This repository provides supplementary material for our paper HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifi…☆21May 8, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Tool to fetch and parse data about Efabless MPW projects☆15Jan 10, 2023Updated 3 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆41Aug 15, 2025Updated 9 months ago
- OpenROAD Agent. This repository contain the model to train and testing the model using EDA Corpus dataset.☆29Jul 24, 2025Updated 10 months ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆292May 9, 2026Updated 2 weeks ago
- RTLMeter benchmark suite☆31May 12, 2026Updated 2 weeks ago
- ☆10Apr 8, 2025Updated last year
- A well-posed RRAM SPICE model implemented in Verilog-A, based on Stanford/ASU filamentary model, using code developed at UC Berkeley☆13Nov 30, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆47Mar 2, 2023Updated 3 years ago
- A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. …☆11May 4, 2022Updated 4 years ago
- AVR CPU Core Implementation in Verilog HDL.☆15Oct 28, 2018Updated 7 years ago
- 不围棋c语言实现,大一大作业,关键算法是判断围棋中的气☆10Aug 14, 2020Updated 5 years ago
- A Verilog Synthesis Regression Test☆37Jan 19, 2026Updated 4 months ago
- MentorGraphics KeyGen & Patch Tool☆16Feb 18, 2022Updated 4 years ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆39Jan 13, 2023Updated 3 years ago
- 复旦数字集成电路设计自动化项目文档☆10Apr 12, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- (Machine) Learning to Do More with Less☆14Jun 11, 2018Updated 7 years ago
- ☆27Aug 2, 2021Updated 4 years ago
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆57May 4, 2026Updated 3 weeks ago
- Design of a 32-kbit synchronous SRAM with 32-bit words, using 180 nm process technology. Developed MATLAB scripts to evaluate architectu…☆16Apr 28, 2021Updated 5 years ago
- A bit-serial CPU☆20Sep 29, 2019Updated 6 years ago
- CERN PyTorch Tutorial for Jet Images generation with GANs☆10Apr 11, 2018Updated 8 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- libView is a GUI tool for library file cell information view and comparison.☆26Jul 24, 2023Updated 2 years ago
- The PS-FPGA project (top level)☆26May 12, 2021Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Berkeley Analog Generator☆16Apr 3, 2019Updated 7 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆16Apr 17, 2021Updated 5 years ago
- ☆20Mar 1, 2021Updated 5 years ago
- AllPix is a powerful tool for various simulation goals with pixel detectors, see the Twiki page for more details☆14Feb 20, 2019Updated 7 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆15Jul 31, 2024Updated last year
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago