Alternatives and similar repositories for asap7_snps

Users that are interested in asap7_snps are comparing it to the libraries listed below

• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆43Updated 2 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆18Updated 5 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆54Updated 2 years ago
• pulp-platform / ELAU
  ☆20Updated last year
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆51Updated 5 years ago
• mflowgen / skywater-130nm
  ASIC Design kit for Skywater 130 for use with mflowgen
  ☆13Updated 2 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 7 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆57Updated 3 months ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 7 years ago
• pulp-platform / svase
  ☆33Updated 10 months ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆38Updated 2 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆92Updated last year
• verilator / rtlmeter
  RTLMeter benchmark suite
  ☆28Updated 3 weeks ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆36Updated 3 months ago
• The-OpenROAD-Project / asap5
  ☆35Updated 2 years ago
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆23Updated 2 years ago
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆16Updated 5 years ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆41Updated last week
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆34Updated 5 months ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated last week
• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆42Updated 2 years ago
• marlls1989 / ascend-freepdk45
  A free standard cell library for SDDS-NCL circuits
  ☆28Updated 2 years ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆21Updated 3 weeks ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆47Updated last year
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• cclienti / svmodule
  SystemVerilog & Verilog Module I/O parser and printer
  ☆25Updated 4 years ago
• aolofsson / IDEA
  ☆33Updated 5 years ago