snishizawa / asap7_snps
Supplemental technology files for ASAP7 PDK with Synopsys design flow
☆13Updated 2 years ago
Alternatives and similar repositories for asap7_snps
Users that are interested in asap7_snps are comparing it to the libraries listed below
Sorting:
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆17Updated 4 years ago
- YosysHQ SVA AXI Properties☆39Updated 2 years ago
- ☆20Updated 3 years ago
- ☆18Updated 10 months ago
- ☆44Updated 5 years ago
- A configurable SRAM generator☆48Updated 4 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- OpenDesign Flow Database☆16Updated 6 years ago
- ☆25Updated 2 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- ☆33Updated 5 years ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- ☆31Updated 4 months ago
- Characterizer☆22Updated last week
- SRAM☆22Updated 4 years ago
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆28Updated 2 weeks ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆83Updated last year
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆30Updated last year
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 3 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- An automatic clock gating utility☆47Updated last month
- NetCracker is an FPGA architecture analysis tool for facilitating the investigation of connectivity patterns within as well as in between…☆17Updated 4 years ago
- Intel's Analog Detailed Router☆38Updated 5 years ago
- An open source generator for standard cell based memories.☆13Updated 8 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆33Updated 3 months ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆26Updated last year
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago