Coarse Grained Reconfigurable Arrays with Chisel3
☆11Jul 1, 2024Updated last year
Alternatives and similar repositories for CGRAs
Users that are interested in CGRAs are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 🎞️ NoC router in Verilog with FIFO☆15Sep 1, 2022Updated 3 years ago
- 🔮 A 16-bit MIPS Processor Implementation in Verilog HDL☆12Aug 30, 2020Updated 5 years ago
- Multi-Dataflow Composer (MDC) design suite☆11Feb 13, 2026Updated 4 months ago
- CGRA framework with vectorization support.☆48Jun 4, 2026Updated 2 weeks ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Jun 7, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆16Nov 12, 2025Updated 7 months ago
- OpenMP front-end based on LLVM for CGRAs☆10Oct 2, 2022Updated 3 years ago
- An Open-Source Tool for CGRA Accelerators☆84Mar 30, 2026Updated 2 months ago
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated 3 months ago
- Documentation for the entire CGRAFlow☆19Sep 17, 2021Updated 4 years ago
- Fast PnR toolchain for CGRA☆18Jul 26, 2024Updated last year
- ☆14Nov 9, 2023Updated 2 years ago
- Zeonica is a simulator for CGRA and Wafer-Scale Accelerators.☆20Jun 10, 2026Updated last week
- Exome Copy Number Variation Polisher via Deep Learning☆18Jun 1, 2020Updated 6 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A language and toolset for implementing dataflow applications on FPGAs☆28Mar 19, 2026Updated 2 months ago
- Release of stream-specialization software/hardware stack.☆124May 5, 2023Updated 3 years ago
- 🗣 Chatroom in Rust☆14Oct 21, 2019Updated 6 years ago
- ☆18Nov 4, 2024Updated last year
- DeepND ASD & ID☆12Apr 29, 2022Updated 4 years ago
- ☆17Apr 7, 2022Updated 4 years ago
- Qingnang Smart Diagnosis is an end-to-end AI healthcare framework with field-proven application capabilities, designed to provide efficie…☆21Jun 4, 2026Updated 2 weeks ago
- Useful Layers for Knet☆21Aug 8, 2021Updated 4 years ago
- ☆15Mar 17, 2026Updated 3 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆16Jul 21, 2024Updated last year
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆174Mar 4, 2026Updated 3 months ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago
- The open-sourced version of BOOM-Explorer☆51May 31, 2023Updated 3 years ago
- Learning to Generate UTR Sequences for Optimized Ribosome Load and Gene Expression☆23May 11, 2025Updated last year
- An Open-Hardware CGRA for accelerated computation on the edge.☆52Oct 31, 2025Updated 7 months ago
- ☆11Aug 4, 2022Updated 3 years ago
- ☆21Oct 15, 2015Updated 10 years ago
- DRA+RISC-V Exploration Framework☆21Jan 8, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Template-based Reconfigurable Architecture Modeling Framework☆14Aug 16, 2022Updated 3 years ago
- Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research☆17Jan 21, 2024Updated 2 years ago
- Memory Compiler Tutorial☆14Oct 7, 2020Updated 5 years ago
- Simulator for MIPS instruction set architecture using pipelining☆14Apr 29, 2016Updated 10 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆81Jan 6, 2026Updated 5 months ago
- ☆18May 1, 2020Updated 6 years ago
- ☆15Jan 19, 2024Updated 2 years ago