Alternatives and similar repositories for hls-llvm-project

Users that are interested in hls-llvm-project are comparing it to the libraries listed below

• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆72Updated 3 weeks ago
• lana555 / dynamatic
  ☆86Updated last year
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆30Updated 3 weeks ago
• esl-epfl / OpenEdgeCGRA
  An Open-Hardware CGRA for accelerated computation on the edge.
  ☆28Updated 8 months ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆129Updated last week
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆39Updated 4 months ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆50Updated 7 years ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆59Updated 7 months ago
• TeCSAR-UNCC / gem5-SALAM
  ☆91Updated last year
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆83Updated last year
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆65Updated last month
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆68Updated last year
• Xilinx / merlin-compiler
  ☆58Updated last year
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆62Updated 2 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆53Updated 2 months ago
• wincle626 / HLS_Legup
  ☆27Updated 7 years ago
• tancheng / CGRA-Bench
  ☆15Updated 2 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆89Updated 2 months ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆56Updated 3 years ago
• icgrp / hipr
  ☆15Updated 2 years ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆68Updated 11 months ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆49Updated last year
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• pku-liang / ksim
  ☆41Updated 4 months ago
• pnnl / soda-opt
  ☆44Updated last week
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆46Updated 2 months ago
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆14Updated 2 years ago
• icgrp / pld2022
  ☆15Updated 2 years ago