cr1901 / spi_tbLinks
CPOL=0, CPHA=0 SPI core for practicing formal verification with yosys
☆21Updated 5 years ago
Alternatives and similar repositories for spi_tb
Users that are interested in spi_tb are comparing it to the libraries listed below
Sorting:
- 妖刀夢渡☆59Updated 6 years ago
- ☆25Updated 6 years ago
- Experiments with Yosys cxxrtl backend☆49Updated 6 months ago
- Tools and Examples for IcoBoard☆80Updated 4 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated last year
- iCE40 floorplan viewer☆24Updated 7 years ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆44Updated 2 months ago
- Ultimate ECP5 development board☆111Updated 6 years ago
- Cross compile FPGA tools☆21Updated 4 years ago
- Board and connector definition files for nMigen☆30Updated 4 years ago
- I want to learn [n]Migen.☆42Updated 5 years ago
- My pergola FPGA projects☆30Updated 4 years ago
- Resource-efficient 16-bit CPU architecture for FPGA control plane☆96Updated 5 months ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆97Updated 2 years ago
- PicoRV☆44Updated 5 years ago
- Industry standard I/O for nMigen☆12Updated 5 years ago
- Industry standard I/O for Amaranth HDL☆29Updated 9 months ago
- Example litex Risc-V SOC and some example code projects in multiple languages.☆68Updated 2 years ago
- Small footprint and configurable HyperBus core☆13Updated 3 years ago
- lightweight open HLS for FPGA rapid prototyping☆20Updated 7 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 7 years ago
- A configurable USB 2.0 device core☆31Updated 5 years ago
- Project Trellis database☆13Updated last year
- USB Full-Speed core written in migen/LiteX☆12Updated 5 years ago
- Hot Reconfiguration Technology demo☆40Updated 2 years ago
- A repo of basic Verilog/SystemVerilog modules useful in other circuits.☆21Updated 7 years ago
- ☆61Updated last year
- Change part number or package in a Xilinx 7-series FPGA bitstream☆39Updated 5 years ago
- DDR3 controller for nMigen (WIP)☆14Updated last year
- USB Full-Speed core written in migen/LiteX☆42Updated 6 years ago