Alternatives and similar repositories for NetCracker

Users that are interested in NetCracker are comparing it to the libraries listed below

• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆27Updated 2 years ago
• pulp-platform / svase
  ☆32Updated 5 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆83Updated last year
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆48Updated last month
• rahulk29 / sram22
  A configurable SRAM generator
  ☆50Updated last week
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• Coloquinte / moosic-yosys-plugin
  Yosys plugin for logic locking and supply-chain security
  ☆22Updated 2 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆39Updated 2 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆29Updated 10 months ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆48Updated 2 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆41Updated 2 years ago
• snishizawa / libretto
  Characterizer
  ☆23Updated 2 weeks ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆30Updated last month
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆49Updated 6 months ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆29Updated 2 months ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆27Updated 4 years ago
• pulp-platform / artistic
  An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
  ☆14Updated last month
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 7 months ago
• UofT-HPRC / Tbps_CRC
  A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second
  ☆15Updated last year
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆46Updated 2 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆105Updated 3 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆83Updated last month
• epfl-vlsc / bitfiltrator
  Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats
  ☆42Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆68Updated 9 months ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆43Updated 4 months ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago