adbrant / zuma-fpgaLinks
Fine Grain FPGA Overlay Architecture and Tools
☆28Updated 4 years ago
Alternatives and similar repositories for zuma-fpga
Users that are interested in zuma-fpga are comparing it to the libraries listed below
Sorting:
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 6 years ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆65Updated 2 years ago
- Mutation Cover with Yosys (MCY)☆90Updated 2 weeks ago
- Mathematical Functions in Verilog☆96Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- A library and command-line tool for querying a Verilog netlist.☆29Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- hardware library for hwt (= ipcore repo)☆43Updated last month
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆47Updated last month
- Python interface to FPGA interchange format☆41Updated 3 years ago
- ☆56Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- ☆109Updated 6 years ago
- A flexible framework for analyzing and transforming FPGA netlists. Official repository.☆104Updated 11 months ago
- WAL enables programmable waveform analysis.☆163Updated 2 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated last year
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆128Updated 8 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.☆66Updated 3 months ago
- ☆114Updated 4 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆122Updated 4 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated 2 months ago
- ☆38Updated 3 years ago