adbrant / zuma-fpgaLinks
Fine Grain FPGA Overlay Architecture and Tools
☆26Updated 3 years ago
Alternatives and similar repositories for zuma-fpga
Users that are interested in zuma-fpga are comparing it to the libraries listed below
Sorting:
- Xilinx Unisim Library in Verilog☆85Updated 5 years ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆61Updated 2 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆65Updated 5 years ago
- A Tcl-based CAD Tool Framework for Xilinx's Vivado Design Suite☆43Updated 5 years ago
- Mutation Cover with Yosys (MCY)☆87Updated 3 weeks ago
- Mathematical Functions in Verilog☆95Updated 4 years ago
- A flexible framework for analyzing and transforming FPGA netlists. Official repository.☆99Updated 7 months ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- A library and command-line tool for querying a Verilog netlist.☆28Updated 3 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.☆62Updated 3 weeks ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Tools for working with circuits as graphs in python☆124Updated last year
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆124Updated last year
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- ☆105Updated 5 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆39Updated 3 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆75Updated 2 months ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆65Updated this week
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- Demo SoC for SiliconCompiler.☆61Updated last week
- Debuggable hardware generator☆70Updated 2 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆217Updated 2 weeks ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- ☆26Updated 2 years ago
- A Vivado HLS Command Line Helper Tool☆36Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆43Updated 5 years ago