Alternatives and similar repositories for zuma-fpga

Users that are interested in zuma-fpga are comparing it to the libraries listed below

• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆50Updated 10 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆91Updated 6 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆88Updated 2 weeks ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆66Updated 5 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆87Updated 5 years ago
• byuccl / spydrnet
  A flexible framework for analyzing and transforming FPGA netlists. Official repository.
  ☆102Updated 9 months ago
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆39Updated 8 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆43Updated 2 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆28Updated 3 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆50Updated 3 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated 2 weeks ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 8 months ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆98Updated 3 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆95Updated 4 years ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• efabless / proton
  ☆33Updated 5 years ago
• FPGA-Research / fos
  FOS - FPGA Operating System
  ☆73Updated 5 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• rubund / graywolf
  ☆113Updated 4 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆88Updated last year
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆63Updated 2 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆86Updated 4 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆68Updated last year
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated last year
• pkuzjx / eda-collection
  ☆107Updated 5 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆119Updated 2 years ago
• idea-fasoc / fasoc
  ☆56Updated 2 years ago