Alternatives and similar repositories for zuma-fpga

Users that are interested in zuma-fpga are comparing it to the libraries listed below

• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated 2 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆41Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 9 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆49Updated 6 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆22Updated 5 years ago
• idea-fasoc / fasoc
  ☆54Updated last year
• aolofsson / POSH
  ☆44Updated 5 years ago
• pkuzjx / eda-collection
  ☆105Updated 5 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• aziesemer / astran
  ASTRAN - Automatic Synthesis of Transistor Networks
  ☆60Updated 3 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆48Updated 4 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆35Updated 5 months ago
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆25Updated 5 months ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 4 years ago
• fukatani / Pyverilog_toolbox
  ☆40Updated 6 years ago
• aolofsson / IDEA
  ☆33Updated 5 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆47Updated last month
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆32Updated last year
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆48Updated 2 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated 10 months ago
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆58Updated 6 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆54Updated last week
• pulp-platform / svase
  ☆31Updated 4 months ago
• Ghonimo / Formal-Verification-With-VC-Formal--Tutorials-and-Examples
  This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…
  ☆27Updated last year