Alternatives and similar repositories for riscy

Users that are interested in riscy are comparing it to the libraries listed below

• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆156Updated 4 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆93Updated 8 months ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆104Updated 9 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆65Updated 5 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆174Updated 3 weeks ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆138Updated 8 months ago
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆64Updated 3 weeks ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 8 years ago
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆57Updated 4 years ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆124Updated last year
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 5 years ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆87Updated 2 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 4 years ago
• intel / aib-phy-hardware
  ☆66Updated 2 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆57Updated 5 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆141Updated this week
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• ucb-bar / sha3
  ☆81Updated last year
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆151Updated 6 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆195Updated 10 months ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated 2 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆99Updated 6 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆139Updated this week