csail-csg / riscyLinks
Riscy Processors - Open-Sourced RISC-V Processors
☆73Updated 6 years ago
Alternatives and similar repositories for riscy
Users that are interested in riscy are comparing it to the libraries listed below
Sorting:
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- Yet Another RISC-V Implementation☆97Updated 11 months ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Bluespec BSV HLHDL tutorial☆108Updated 9 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆102Updated 6 years ago
- Chisel components for FPGA projects☆126Updated 2 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated last month
- Main page☆128Updated 5 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 4 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆162Updated 5 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- ☆88Updated 2 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆172Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆140Updated 11 months ago
- OmniXtend cache coherence protocol☆82Updated 3 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- Lipsi: Probably the Smallest Processor in the World☆86Updated last year
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- For contributions of Chisel IP to the chisel community.☆65Updated 10 months ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆124Updated 4 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated this week
- Connectal is a framework for software-driven hardware development.☆172Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆109Updated 4 years ago
- Provides various testers for chisel users☆100Updated 2 years ago