csail-csg / riscyLinks
Riscy Processors - Open-Sourced RISC-V Processors
☆73Updated 6 years ago
Alternatives and similar repositories for riscy
Users that are interested in riscy are comparing it to the libraries listed below
Sorting:
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- Yet Another RISC-V Implementation☆98Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- Bluespec BSV HLHDL tutorial☆110Updated 9 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 5 months ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆104Updated 6 years ago
- Main page☆128Updated 5 years ago
- Chisel components for FPGA projects☆127Updated 2 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆148Updated 2 months ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆164Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆172Updated 5 years ago
- Lipsi: Probably the Smallest Processor in the World☆88Updated last year
- SoCRocket - Core Repository☆38Updated 8 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆67Updated 11 months ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- ☆67Updated 2 years ago
- ☆88Updated 2 years ago
- A dynamic verification library for Chisel.☆156Updated 11 months ago
- Provides various testers for chisel users☆100Updated 2 years ago