Riscy Processors - Open-Sourced RISC-V Processors
☆74Apr 4, 2019Updated 7 years ago
Alternatives and similar repositories for riscy
Users that are interested in riscy are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Sep 15, 2017Updated 8 years ago
- An executable specification of the RISCV ISA in L3.☆44Mar 1, 2019Updated 7 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆170Jul 3, 2020Updated 6 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆35Jul 10, 2016Updated 10 years ago
- Open Analog Design Environment☆26May 19, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆224Jan 23, 2020Updated 6 years ago
- SoftCPU/SoC engine-V☆56Apr 28, 2026Updated 3 months ago
- A generic test bench written in Bluespec☆57Dec 15, 2020Updated 5 years ago
- A formal semantics of the RISC-V ISA in Haskell☆176Aug 13, 2023Updated 3 years ago
- Mini RISC-V SOC☆13Nov 13, 2015Updated 10 years ago
- Connectal is a framework for software-driven hardware development.☆180Oct 16, 2023Updated 2 years ago
- Common RTL blocks used in SiFive's projects☆194May 13, 2022Updated 4 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Oct 5, 2017Updated 8 years ago
- Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory…☆31Oct 18, 2018Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆19Dec 15, 2023Updated 2 years ago
- Hardware-accelerated sorting algorithm☆16May 4, 2020Updated 6 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆17Jul 17, 2016Updated 10 years ago
- Bluespec SystemVerilog library for use of the IBM Coherent Accelerator-Processor Interface (CAPI)