csail-csg / riscyLinks
Riscy Processors - Open-Sourced RISC-V Processors
☆73Updated 6 years ago
Alternatives and similar repositories for riscy
Users that are interested in riscy are comparing it to the libraries listed below
Sorting:
- Yet Another RISC-V Implementation☆99Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Chisel components for FPGA projects☆127Updated 2 years ago
- Bluespec BSV HLHDL tutorial☆110Updated 9 years ago
- Main page☆128Updated 5 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆178Updated 6 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 weeks ago
- SoCRocket - Core Repository☆38Updated 8 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated last month
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆104Updated 7 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆149Updated last week
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆67Updated last year
- ☆67Updated 2 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- ☆88Updated 2 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆173Updated 5 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆123Updated 4 months ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 5 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- Connectal is a framework for software-driven hardware development.☆176Updated 2 years ago
- Lipsi: Probably the Smallest Processor in the World☆88Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago