csail-csg / riscyLinks
Riscy Processors - Open-Sourced RISC-V Processors
☆74Updated 6 years ago
Alternatives and similar repositories for riscy
Users that are interested in riscy are comparing it to the libraries listed below
Sorting:
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆175Updated last month
- Yet Another RISC-V Implementation☆93Updated 9 months ago
- RISC-V Formal Verification Framework☆141Updated last week
- RiscyOO: RISC-V Out-of-Order Processor☆158Updated 4 years ago
- Bluespec BSV HLHDL tutorial☆105Updated 9 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 8 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Main page☆126Updated 5 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆142Updated 3 weeks ago
- Chisel components for FPGA projects☆124Updated last year
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- Lipsi: Probably the Smallest Processor in the World☆86Updated last year
- Provides various testers for chisel users☆100Updated 2 years ago
- FGPU is a soft GPU architecture general purpose computing☆57Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated last month
- A dynamic verification library for Chisel.☆151Updated 7 months ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- Provides dot visualizations of chisel/firrtl circuits☆119Updated 2 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- OmniXtend cache coherence protocol☆82Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated last month
- (System)Verilog to Chisel translator☆114Updated 3 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆138Updated 9 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆165Updated this week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago