rdolbeau / VexRiscvBPluginGeneratorLinks
☆18Updated 3 years ago
Alternatives and similar repositories for VexRiscvBPluginGenerator
Users that are interested in VexRiscvBPluginGenerator are comparing it to the libraries listed below
Sorting:
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated last year
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆31Updated 4 years ago
- Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.☆27Updated 4 years ago
- OmniXtend cache coherence protocol☆82Updated 6 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆71Updated last year
- ☆38Updated 3 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- RISC-V Nox core☆70Updated 4 months ago
- RISC-V Nexus Trace TG documentation and reference code☆55Updated 11 months ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆69Updated last year
- A simple AXI4 DMA unit written in SpinalHDL.☆18Updated 5 years ago
- ☆37Updated last year
- Naive Educational RISC V processor☆92Updated 2 months ago
- ☆20Updated this week
- ☆10Updated 3 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- ☆20Updated last month
- Chisel Cheatsheet☆34Updated 2 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- RISC-V processor☆32Updated 3 years ago