rsnikhil / RISCV_Piccolo_v1Links
Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
☆33Updated 8 years ago
Alternatives and similar repositories for RISCV_Piccolo_v1
Users that are interested in RISCV_Piccolo_v1 are comparing it to the libraries listed below
Sorting:
- SoftCPU/SoC engine-V☆54Updated 2 months ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Yet Another RISC-V Implementation☆93Updated 8 months ago
- Riscy Processors - Open-Sourced RISC-V Processors☆74Updated 6 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Demo SoC for SiliconCompiler.☆59Updated last week
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 6 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- CMod-S6 SoC☆42Updated 7 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- ☆63Updated 6 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 10 months ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated last week
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- FGPU is a soft GPU architecture general purpose computing☆57Updated 4 years ago
- Platform Level Interrupt Controller☆40Updated last year
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- SoCRocket - Core Repository☆37Updated 8 years ago
- A RISC-V processor☆15Updated 6 years ago
- ☆46Updated 3 weeks ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆89Updated 5 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago