Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
☆35Jul 10, 2016Updated 9 years ago
Alternatives and similar repositories for RISCV_Piccolo_v1
Users that are interested in RISCV_Piccolo_v1 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆43May 3, 2026Updated last month
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆14Jan 4, 2021Updated 5 years ago
- Formal specification of RISC-V Instruction Set☆102Jun 29, 2020Updated 6 years ago
- "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)☆19Sep 26, 2024Updated last year
- A RISC-V processor☆15Dec 11, 2018Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Riscy Processors - Open-Sourced RISC-V Processors☆74Apr 4, 2019Updated 7 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆39Mar 30, 2021Updated 5 years ago
- ☆65Dec 16, 2018Updated 7 years ago
- An experimental CPU design☆15Feb 9, 2020Updated 6 years ago
- A simple RISC-V core, described with Verilog☆27Jun 1, 2013Updated 13 years ago
- A small 32-bit implementation of the RISC-V architecture☆33Apr 10, 2026Updated 2 months ago
- An FPGA in your USB Port☆11Jul 1, 2021Updated 4 years ago
- Mini RISC-V SOC☆13Nov 13, 2015Updated 10 years ago
- Resources from my class on computer architecture design☆10Apr 25, 2018Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Atom Hardware IDE☆13May 4, 2021Updated 5 years ago
- general-cores☆21Jul 16, 2025Updated 11 months ago
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆424Jun 9, 2026Updated 2 weeks ago
- RISC-V CPU Core☆439Jun 24, 2025Updated last year
- A extremely size-optimized RV32I soft processor for FPGA.☆27Jun 19, 2018Updated 8 years ago
- uRV RISC-V core☆19Sep 29, 2015Updated 10 years ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆379Jul 12, 2017Updated 8 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Updated this week
- Yet Another RISC-V Implementation☆99Sep 21, 2024Updated last year
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 5 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆17Jul 17, 2016Updated 9 years ago
- A small RISC-V RV32I core written in VHDL, intended as testbed for my personal VHDL learning☆31May 22, 2018Updated 8 years ago
- RISC-V port of LLVM Linker☆24Aug 3, 2018Updated 7 years ago
- Featherweight RISC-V implementation☆53Jan 17, 2022Updated 4 years ago
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆14Dec 20, 2016Updated 9 years ago
- FIR Filter in Verilog☆15Nov 17, 2019Updated 6 years ago
- Port of https://github.com/eleqian/WiDSO/tree/master/MCU/USB-Blaster to GCC and "traditional" STM32F103C8T6 Bluepill board.☆45Feb 15, 2019Updated 7 years ago
- soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…☆35Dec 11, 2016Updated 9 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A Bluespec SystemVerilog library of miscellaneous components☆18May 19, 2026Updated last month
- RISCV SoftCPU Contest 2018☆14Nov 17, 2018Updated 7 years ago
- The BERI and CHERI processor and hardware platform☆51Mar 27, 2017Updated 9 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Feb 24, 2023Updated 3 years ago
- RISC-V Formal Verification Framework☆633Apr 6, 2022Updated 4 years ago
- RISC-V Frontend Server☆65Mar 31, 2019Updated 7 years ago
- Smol 2-stage RISC-V processor in nMigen☆26May 6, 2021Updated 5 years ago