chiphackers / covered

Related projects ⓘ

Alternatives and complementary repositories for covered

• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated last year
• vsdip / vsdsram_sky130
  ☆39Updated 2 years ago
• pulp-platform / svase
  ☆29Updated 2 months ago
• chipsalliance / UHDM-integration-tests
  ☆30Updated last year
• povik / yosys-slang
  slang-based frontend for Yosys
  ☆43Updated this week
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆25Updated 4 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆15Updated last week
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆23Updated 8 months ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆33Updated last year
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 4 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆43Updated 4 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆32Updated last year
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆80Updated 3 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆46Updated 4 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆59Updated 3 years ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆45Updated 6 months ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆36Updated 3 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆15Updated 6 months ago
• google / globalfoundries-pdks
  Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.
  ☆46Updated 2 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆48Updated 6 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆38Updated 4 years ago
• aolofsson / POSH
  ☆39Updated 4 years ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆21Updated 6 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆35Updated last year
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆31Updated 4 months ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated 10 months ago
• FPGA-Research-Manchester / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆26Updated 3 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year