chiphackers / coveredLinks
Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
☆32Updated 7 years ago
Alternatives and similar repositories for covered
Users that are interested in covered are comparing it to the libraries listed below
Sorting:
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Updated 3 years ago
- ☆41Updated 3 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆72Updated 7 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆29Updated last year
- ☆38Updated 3 years ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- SystemVerilog Linter based on pyslang☆31Updated 9 months ago
- Python script to transform a VCD file to wavedrom format☆84Updated 3 years ago
- Mathematical Functions in Verilog☆96Updated 4 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- Quick'n'dirty FuseSoC+cocotb example☆19Updated last year
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆64Updated last week
- Extensible FPGA control platform☆61Updated 2 years ago
- FPGA250 aboard the eFabless Caravel☆32Updated 5 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 3 months ago
- ☆26Updated 2 years ago
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Updated 4 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- Import and export IP-XACT XML register models☆37Updated 3 months ago
- IP-core package generator for AXI4/Avalon☆22Updated 7 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆56Updated this week
- submission repository for efabless mpw6 shuttle☆31Updated 2 years ago
- A simple DDR3 memory controller☆61Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆82Updated 3 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 6 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆79Updated 5 years ago