jeffreycassidy / BlueLink
Bluespec SystemVerilog library for use of the IBM Coherent Accelerator-Processor Interface (CAPI)
☆11Updated 8 years ago
Alternatives and similar repositories for BlueLink:
Users that are interested in BlueLink are comparing it to the libraries listed below
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated 3 months ago
- Rodinia Benchmark Suite for OpenCL-based FPGAs☆31Updated 2 years ago
- Connectal is a framework for software-driven hardware development.☆168Updated last year
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- ☆87Updated 2 years ago
- The Shang high-level synthesis framework☆119Updated 10 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 8 years ago
- CAPI SNAP Framework Hardware and Software☆110Updated 4 years ago
- A home for Genesis2 sources.☆41Updated this week
- Caribou: Distributed Smart Storage built with FPGAs☆65Updated 6 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- Power Service Layer Simulation Engine☆29Updated 3 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 9 months ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆89Updated last month
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 7 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆74Updated 9 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆74Updated 6 years ago
- A parallel and distributed simulator for thousand-core chips☆24Updated 7 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆141Updated 3 weeks ago
- A polyhedral compiler for hardware accelerators☆56Updated 9 months ago
- The Task Parallel System Composer (TaPaSCo)☆108Updated 3 months ago
- ☆12Updated 9 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆49Updated 6 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 years ago
- OmniXtend cache coherence protocol☆82Updated 4 years ago
- A Language for Closed-form High-level ARchitecture Modeling☆20Updated 5 years ago
- Support for Rocket Chip on Zynq FPGAs☆40Updated 6 years ago