kkiningh / rules_verilator

Related projects ⓘ

Alternatives and complementary repositories for rules_verilator

• Lightelligence / rules_verilog
  Bazel build rules for compiling Verilog
  ☆21Updated 8 months ago
• hdl / bazel_rules_hdl
  Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…
  ☆116Updated this week
• sifive / duh
  👾 Design ∪ Hardware
  ☆72Updated last week
• Kuree / hgdb
  Hardware generator debugger
  ☆71Updated 9 months ago
• chipsalliance / fpga-interchange-schema
  ☆51Updated 2 years ago
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 2 years ago
• mattvenn / instrumented_adder
  Instrumenting adders to measure speed
  ☆13Updated 2 years ago
• agoessling / rules_vivado
  Bazel rules for Xilinx Vivado
  ☆18Updated 2 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆51Updated 3 weeks ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆34Updated 7 months ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆42Updated 7 months ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆27Updated last week
• Kuree / kratos
  Debuggable hardware generator
  ☆67Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆77Updated last week
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆16Updated 2 years ago
• pieter3d / simview
  ☆76Updated 8 months ago
• sifive / chisel-circt
  Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
  ☆70Updated last year
• djg / verilated-rs
  Verilator Porcelain
  ☆37Updated last year
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆56Updated this week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆105Updated 2 years ago
• byuccl / bfat
  Bitstream Fault Analysis Tool
  ☆13Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆55Updated last week
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆29Updated last month
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆40Updated 3 months ago
• masc-ucsc / fluid
  Fluid Pipelines
  ☆11Updated 6 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆33Updated 4 years ago
• Raamakrishnan / verilog-filelist-parser
  A Verilog Filelist parser in Rust
  ☆9Updated 2 years ago
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆46Updated last year
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆71Updated last month
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆46Updated 10 months ago