kkiningh / rules_verilatorLinks
Bazel build rules for Verilator
☆24Updated last year
Alternatives and similar repositories for rules_verilator
Users that are interested in rules_verilator are comparing it to the libraries listed below
Sorting:
- Bazel build rules for compiling Verilog☆21Updated last year
- Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…☆144Updated last month
- firrtlator is a FIRRTL C++ library☆23Updated 8 years ago
- Hardware generator debugger☆76Updated last year
- Mutation Cover with Yosys (MCY)☆88Updated 2 weeks ago
- A Verilog Synthesis Regression Test☆37Updated last year
- ABC: System for Sequential Logic Synthesis and Formal Verification☆29Updated 2 weeks ago
- Fiber-based SystemVerilog Simulator.☆25Updated 3 years ago
- ☆104Updated 3 years ago
- The specification for the FIRRTL language☆62Updated this week
- FPGA Assembly (FASM) Parser and Generator☆97Updated 3 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆49Updated 2 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆37Updated this week
- A Verilog Filelist parser in Rust☆11Updated 3 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- ☆56Updated 3 years ago
- Chisel/Firrtl execution engine☆153Updated last year
- Debuggable hardware generator☆70Updated 2 years ago
- BSC Development Workstation (BDW)☆32Updated last year
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 5 years ago
- Collection of test cases for Yosys☆17Updated 3 years ago
- Bazel rules for Xilinx Vivado☆20Updated 3 years ago
- Testing processors with Random Instruction Generation☆48Updated 3 weeks ago
- A SystemVerilog language server based on the Slang library.☆53Updated last week
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language☆91Updated last week
- mantle library☆44Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated last month
- ☆85Updated 2 weeks ago