Bryce-Readyhough / caravel_UNCC_MPW_1
This is the Google/EFabless/Skywater Caravel submission of an Analog Spiking Neuron Circuit. The submission also includes a SONOS transistor array.
☆11Updated last year
Alternatives and similar repositories for caravel_UNCC_MPW_1:
Users that are interested in caravel_UNCC_MPW_1 are comparing it to the libraries listed below
- Space CACD☆12Updated 5 years ago
- FPGA250 aboard the eFabless Caravel☆29Updated 4 years ago
- LibreSilicon's Standard Cell Library Generator☆18Updated 11 months ago
- ☆36Updated 2 years ago
- ☆16Updated 4 months ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆12Updated 4 years ago
- SRAM☆8Updated 4 years ago
- Source-Opened RISCV for Crypto☆15Updated 3 years ago
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- IRSIM switch-level simulator for digital circuits☆32Updated 11 months ago
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆11Updated 4 years ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆19Updated 3 weeks ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆31Updated 2 weeks ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- ☆18Updated 4 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆27Updated 2 months ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆22Updated 4 years ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆13Updated 4 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- KLayout technology files for ASAP7 FinFET educational process☆20Updated 2 years ago
- ☆18Updated 5 months ago
- Theia: ray graphic processing unit☆20Updated 10 years ago
- Ubuntu scripts that are used for setting up your machine for Sky130 designs.☆17Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆40Updated last year
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆16Updated last year