openrisc / orpsoc-coresLinks
Core description files for FuseSoC
☆124Updated 4 years ago
Alternatives and similar repositories for orpsoc-cores
Users that are interested in orpsoc-cores are comparing it to the libraries listed below
Sorting:
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- An Open Source configuration of the Arty platform☆129Updated last year
- MIPSfpga+ allows loading programs via UART and has a switchable clock☆109Updated 5 years ago
- Yet Another RISC-V Implementation☆94Updated 9 months ago
- FuseSoC standard core library☆143Updated 3 weeks ago
- A utility for Composing FPGA designs from Peripherals☆179Updated 6 months ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆96Updated 3 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆74Updated 6 years ago
- A 32-bit RISC-V processor for mriscv project☆58Updated 7 years ago
- OpenRISC 1200 implementation☆170Updated 9 years ago
- ☆113Updated 4 years ago
- Python tools for Vivado Projects☆73Updated 6 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆101Updated 6 years ago
- A 32-bit Microcontroller featuring a RISC-V core☆153Updated 7 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- The OpenRISC 1000 architectural simulator☆76Updated last month
- LatticeMico32 soft processor☆106Updated 10 years ago
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 3 months ago
- Verilog implementation of a RISC-V core☆118Updated 6 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 8 years ago
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆413Updated 2 weeks ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆123Updated 8 years ago
- Collection of open-source peripherals in Verilog☆178Updated 3 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- The original high performance and small footprint system-on-chip based on Migen™☆328Updated last month
- Featherweight RISC-V implementation☆52Updated 3 years ago
- A wishbone controlled scope for FPGA's☆82Updated last year