Alternatives and similar repositories for orpsoc-cores

Users that are interested in orpsoc-cores are comparing it to the libraries listed below

• onchipuis / mriscv
  A 32-bit Microcontroller featuring a RISC-V core
  ☆159Updated 7 years ago
• onchipuis / mriscvcore
  A 32-bit RISC-V processor for mriscv project
  ☆60Updated 8 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆176Updated 10 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆185Updated last year
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 8 years ago
• rubund / graywolf
  ☆114Updated 4 years ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆131Updated last year
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆99Updated 6 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 6 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆105Updated 7 years ago
• MIPSfpga / mipsfpga-plus
  MIPSfpga+ allows loading programs via UART and has a switchable clock
  ☆111Updated 6 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• steveicarus / ivtest
  Regression test suite for Icarus Verilog. (OBSOLETE)
  ☆115Updated 2 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆107Updated 11 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆77Updated 7 months ago
• swetland / zynq-sandbox
  a playground for xilinx zynq fpga experiments
  ☆49Updated 7 years ago
• westerndigitalcorporation / swerv-ISS
  Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
  ☆202Updated 5 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆150Updated 2 weeks ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 9 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆44Updated 7 years ago
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 3 years ago
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆176Updated 2 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆125Updated 9 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 6 years ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆67Updated 6 years ago
• f32c / f32c
  A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
  ☆412Updated last month