openrisc / orpsoc-coresLinks
Core description files for FuseSoC
☆124Updated 5 years ago
Alternatives and similar repositories for orpsoc-cores
Users that are interested in orpsoc-cores are comparing it to the libraries listed below
Sorting:
- OpenRISC 1200 implementation☆178Updated 10 years ago
- A utility for Composing FPGA designs from Peripherals☆186Updated last year
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- A 32-bit RISC-V processor for mriscv project☆60Updated 8 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 6 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- ☆114Updated 5 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- The OpenRISC 1000 architectural simulator☆77Updated 9 months ago
- MIPSfpga+ allows loading programs via UART and has a switchable clock☆111Updated 6 years ago
- A 32-bit Microcontroller featuring a RISC-V core☆160Updated 7 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆106Updated 7 years ago
- Connectal is a framework for software-driven hardware development.☆176Updated 2 years ago
- An Open Source configuration of the Arty platform☆131Updated 2 years ago
- ☆63Updated 7 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆125Updated 9 years ago
- FuseSoC standard core library☆151Updated last month
- LatticeMico32 soft processor☆107Updated 11 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator☆202Updated 5 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆72Updated 7 years ago
- Featherweight RISC-V implementation☆53Updated 4 years ago
- Python tools for Vivado Projects☆72Updated 6 years ago
- CMod-S6 SoC☆45Updated 8 years ago
- RISC-V Frontend Server☆64Updated 6 years ago