Alternatives and similar repositories for Alliance-VLSI-CAD-System

Users that are interested in Alliance-VLSI-CAD-System are comparing it to the libraries listed below

• zylin / Verilog_VCD
  https://pypi.python.org/pypi/Verilog_VCD
  ☆23Updated 8 years ago
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆39Updated 8 years ago
• The-OpenROAD-Project / OpenROAD-Cloud
  The source code that empowers OpenROAD Cloud
  ☆12Updated 5 years ago
• tclarke / sky130radio
  components and examples for creating radio ICs using the open skywater 130nm PDK
  ☆19Updated 4 years ago
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆25Updated 3 months ago
• rubund / graywolf
  ☆112Updated 4 years ago
• mabrains / OpenAnalogDesign
  Open Analog Design Environment
  ☆24Updated 2 years ago
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated last year
• steveicarus / ivtest
  Regression test suite for Icarus Verilog. (OBSOLETE)
  ☆115Updated 2 years ago
• Coloquinte / Coloquinte_placement
  An analytical VLSI placer
  ☆28Updated 3 years ago
• idea-fasoc / fasoc
  ☆56Updated 2 years ago
• Qucs / ADMS
  ADMS is a code generator for some of Verilog-A
  ☆101Updated 2 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆48Updated 4 months ago
• mabrains / sky130_ubuntu_setup
  Ubuntu scripts that are used for setting up your machine for Sky130 designs.
  ☆18Updated 4 years ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆55Updated 6 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• efabless / ravenna
  32-bit RISC-V microcontroller
  ☆11Updated 4 years ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆20Updated 2 weeks ago
• YosysHQ / sby-gui
  GUI for SymbiYosys
  ☆17Updated this week
• USCPOSH / AMS_KGD
  A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.
  ☆36Updated 4 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆22Updated 6 years ago
• parallella / openeda
  Open source EDA chip design flow
  ☆51Updated 8 years ago
• Qucs / gnucsator
  This package provides a gnucap based qucsator implementation.
  ☆14Updated 2 months ago
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 5 years ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated 6 months ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 5 years ago
• onchipuis / mriscvcore
  A 32-bit RISC-V processor for mriscv project
  ☆59Updated 8 years ago
• Gordonei / MyHDL-based-FPGA-DSP-Toolflow
  A library for generating Software Defined Radio-intended DSP code for FPGAs that makes use of the MyHDL (www.myhdl.org) Python library. T…
  ☆24Updated 13 years ago
• efabless / raptor
  Arm Cortex-M0 based Customizable SoC for IoT Applications
  ☆15Updated 4 years ago