Open Analog Design Environment
☆25May 19, 2023Updated 2 years ago
Alternatives and similar repositories for OpenAnalogDesign
Users that are interested in OpenAnalogDesign are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Donald Amundson's Python interface to OpenAccess IC design data API☆18Apr 23, 2010Updated 15 years ago
- ☆17Nov 4, 2024Updated last year
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Oct 18, 2021Updated 4 years ago
- Guides and templates for using open source RF design tools with the SkyWater SKY130 process.☆19Nov 13, 2020Updated 5 years ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Dec 5, 2022Updated 3 years ago
- KLayout technology files for Skywater SKY130☆44Jul 19, 2023Updated 2 years ago
- ☆25Dec 16, 2020Updated 5 years ago
- Zero to ASIC group submission for MPW2☆13Mar 26, 2025Updated 11 months ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆121Jul 31, 2021Updated 4 years ago
- LibreSilicon's Standard Cell Library Generator☆22Oct 30, 2025Updated 4 months ago
- ☆20Nov 22, 2021Updated 4 years ago
- Completed LDO Design for Skywaters 130nm☆19Feb 16, 2023Updated 3 years ago
- Test Chip General Purpose OpAmp using Skywater SKY130 PDK☆20Mar 1, 2021Updated 5 years ago
- 5 days (30 hours) is all what took me to learn the basics and design a pipelined RV32I core. Check this article to know more !☆12Feb 2, 2022Updated 4 years ago
- Skywater 130nm Klayout Device Generators PDK☆30Jul 12, 2024Updated last year
- gaw3-20200922 fork with patches to improve remote commands sent from xschem to display waveforms☆17Mar 28, 2025Updated 11 months ago
- GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @ https://github.com/google/skywater-pdk☆16Jun 3, 2021Updated 4 years ago
- 8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving…☆14Jul 21, 2022Updated 3 years ago
- VSD workshop - Phase Locked Loop(PLL) IC Design☆15Aug 4, 2021Updated 4 years ago
- This repository contains the design and simulation process and results of potentiometric digital to analog converter.☆15Oct 6, 2020Updated 5 years ago
- SRAM☆22Sep 6, 2020Updated 5 years ago
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆30Jul 30, 2022Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Dec 30, 2022Updated 3 years ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆130Feb 3, 2026Updated last month
- IO and periphery cells for the GF180MCU provided by GlobalFoundries.☆14Dec 3, 2022Updated 3 years ago
- This repository in a walk through the entire process of PLL IC designing from the tools to the final tapeout.☆20Feb 16, 2022Updated 4 years ago
- Ubuntu scripts that are used for setting up your machine for Sky130 designs.☆18Mar 18, 2021Updated 5 years ago
- 7 track standard cells for GF180MCU provided by GlobalFoundries.☆27Dec 1, 2022Updated 3 years ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆108Aug 21, 2024Updated last year
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆29Feb 21, 2019Updated 7 years ago
- Hdl21 Schematics☆16Jan 24, 2024Updated 2 years ago
- ☆30Aug 19, 2019Updated 6 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆38Jun 2, 2021Updated 4 years ago
- Hardware Description Library☆90Feb 17, 2026Updated last month
- Interchange formats for chip design.☆38Feb 15, 2026Updated last month
- ☆30Feb 4, 2021Updated 5 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆79Nov 26, 2020Updated 5 years ago
- ☆24Dec 8, 2021Updated 4 years ago
- https://caravel-user-project.readthedocs.io☆230Feb 25, 2025Updated last year