Alternatives and similar repositories for xge_mac

Users that are interested in xge_mac are comparing it to the libraries listed below

• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 6 years ago
• antmicro / nvme-verilog-pcie
  ☆79Updated 3 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆63Updated 4 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆114Updated 3 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆56Updated 11 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆97Updated 5 years ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆71Updated 2 months ago
• andres-mancera / ethernet_10ge_mac_SV_tb
  SystemVerilog testbench for an Ethernet 10GE MAC core
  ☆46Updated 9 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆60Updated 5 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆158Updated 8 months ago
• VerificationExcellence / SystemVerilogAssertions
  Examples and reference for System Verilog Assertions
  ☆88Updated 8 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆66Updated 5 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆76Updated 11 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆91Updated 3 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆86Updated last year
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆75Updated 5 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆57Updated 4 months ago
• freecores / i2c
  I2C controller core
  ☆46Updated 2 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆15Updated 11 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆43Updated 4 years ago
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆36Updated 8 years ago
• sach / System-Verilog-Packet-Library
  System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers
  ☆77Updated 6 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆48Updated last year
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 7 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year
• aquaxis / gemac
  Gigabit MAC + UDP/TCP/IP offload Engine
  ☆33Updated 6 years ago
• freecores / ddr3_sdram
  DDR3 SDRAM controller
  ☆18Updated 11 years ago
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆59Updated 2 weeks ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆72Updated 5 years ago