mrc-donato / CHIPKIT-TutorialLinks
☆15Updated 4 years ago
Alternatives and similar repositories for CHIPKIT-Tutorial
Users that are interested in CHIPKIT-Tutorial are comparing it to the libraries listed below
Sorting:
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- Next generation CGRA generator☆118Updated last week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Floating point modules for CHISEL☆32Updated 11 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- ☆89Updated last week
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- ☆67Updated 2 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 6 months ago
- ☆29Updated 8 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- DASS HLS Compiler☆29Updated 2 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆61Updated 5 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 3 years ago
- Project repo for the POSH on-chip network generator☆52Updated 9 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- A Rocket-based RISC-V superscalar in-order core☆36Updated 2 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆73Updated last year
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆37Updated 3 months ago
- PACoGen: Posit Arithmetic Core Generator☆75Updated 6 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- CGRA framework with vectorization support.☆42Updated this week
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated last week
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago