mrc-donato / CHIPKIT-Tutorial
☆15Updated 4 years ago
Alternatives and similar repositories for CHIPKIT-Tutorial:
Users that are interested in CHIPKIT-Tutorial are comparing it to the libraries listed below
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 5 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- Project repo for the POSH on-chip network generator☆45Updated last month
- Repo for all activity related to the ODSA Bunch of Wires Specification☆24Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- ☆43Updated 5 years ago
- Next generation CGRA generator☆111Updated this week
- For contributions of Chisel IP to the chisel community.☆61Updated 5 months ago
- ☆55Updated 4 years ago
- A Rocket-based RISC-V superscalar in-order core☆31Updated last week
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 2 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 7 months ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆40Updated last week
- An infrastructure for integrated EDA☆38Updated last year
- ☆66Updated 2 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆38Updated 7 months ago
- ☆57Updated this week
- fakeram generator for use by researchers who do not have access to commercial ram generators☆35Updated 2 years ago
- Floating point modules for CHISEL☆32Updated 10 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- cycle accurate Network-on-Chip Simulator☆27Updated last year
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆34Updated last month
- Public release☆51Updated 5 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆65Updated last year
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago