mrc-donato / CHIPKIT-Tutorial
☆15Updated 3 years ago
Alternatives and similar repositories for CHIPKIT-Tutorial:
Users that are interested in CHIPKIT-Tutorial are comparing it to the libraries listed below
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Tests for example Rocket Custom Coprocessors☆70Updated 5 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆24Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated 2 weeks ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆99Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆37Updated 5 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 6 months ago
- ☆67Updated 2 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆62Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 9 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- For contributions of Chisel IP to the chisel community.☆59Updated 3 months ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated this week
- ☆54Updated this week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- ☆43Updated last week
- Next generation CGRA generator☆110Updated this week
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- Floating point modules for CHISEL☆31Updated 10 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Pure digital components of a UCIe controller☆55Updated this week
- sram/rram/mram.. compiler☆30Updated last year
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated this week
- A DSL for Systolic Arrays☆79Updated 6 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆87Updated 11 months ago