riscveval / Rocket-ChipLinks
☆23Updated 7 years ago
Alternatives and similar repositories for Rocket-Chip
Users that are interested in Rocket-Chip are comparing it to the libraries listed below
Sorting:
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆48Updated 4 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆40Updated last year
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 4 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- Chisel Things for OFDM☆32Updated 5 years ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 5 months ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Updated 5 years ago
- Dual RISC-V DISC with integrated eFPGA☆16Updated 3 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Updated last year
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago
- A DMA Controller for RISCV CPUs☆14Updated 9 years ago
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆20Updated 3 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated last month
- DDR4 Simulation Project in System Verilog☆41Updated 10 years ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆18Updated 11 months ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- ☆33Updated 2 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- OmniXtend cache coherence protocol☆82Updated last month
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆32Updated last month
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- ☆47Updated 2 months ago