riscveval / Rocket-Chip
☆22Updated 7 years ago
Alternatives and similar repositories for Rocket-Chip:
Users that are interested in Rocket-Chip are comparing it to the libraries listed below
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆26Updated 5 years ago
- Platform Level Interrupt Controller☆39Updated 11 months ago
- PCI Express controller model☆55Updated 2 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆47Updated 4 years ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- DDR4 Simulation Project in System Verilog☆39Updated 10 years ago
- ☆25Updated last week
- Hamming ECC Encoder and Decoder to protect memories☆31Updated 2 months ago
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 4 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated this week
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 2 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆20Updated 3 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆61Updated 10 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆38Updated 2 years ago
- ☆54Updated 4 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- RISC-V soft-core PEs for TaPaSCo☆18Updated 10 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 5 months ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last month
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 5 months ago
- Dual RISC-V DISC with integrated eFPGA☆16Updated 3 years ago
- Advanced Debug Interface☆14Updated 2 months ago
- ☆11Updated 3 weeks ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 5 months ago