KireinaHoro / rocket-zynqmpLinks
☆13Updated 4 years ago
Alternatives and similar repositories for rocket-zynqmp
Users that are interested in rocket-zynqmp are comparing it to the libraries listed below
Sorting:
- ☆33Updated 8 months ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆64Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆71Updated last year
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- ☆81Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆107Updated 2 months ago
- AIA IP compliant with the RISC-V AIA spec☆46Updated 10 months ago
- PCI Express controller model☆71Updated 3 years ago
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆24Updated 2 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆30Updated 5 years ago
- ☆69Updated 4 years ago
- Chisel Learning Journey☆111Updated 2 years ago
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆51Updated 4 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆113Updated 2 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆21Updated 7 months ago
- The official NaplesPU hardware code repository☆20Updated 6 years ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆33Updated 5 years ago
- ☆37Updated 7 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 11 months ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆16Updated last year
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated 2 weeks ago
- BlackParrot on Zynq☆47Updated 3 weeks ago
- Wrapper for Rocket-Chip on FPGAs☆138Updated 3 years ago
- ☆89Updated 3 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago