KireinaHoro / rocket-zynqmpLinks
☆13Updated 4 years ago
Alternatives and similar repositories for rocket-zynqmp
Users that are interested in rocket-zynqmp are comparing it to the libraries listed below
Sorting:
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- ☆33Updated 2 months ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- PCI Express controller model☆57Updated 2 years ago
- Chisel Cheatsheet☆33Updated 2 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆17Updated 3 weeks ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆22Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 10 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- ☆31Updated 2 months ago
- ☆36Updated 6 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Support for Rocket Chip on Zynq FPGAs☆40Updated 6 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆32Updated 5 months ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- ☆58Updated 4 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆47Updated 4 years ago
- ☆21Updated 4 years ago
- StateMover is a checkpoint-based debugging framework for FPGAs.☆19Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆56Updated 3 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆35Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated 7 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆28Updated 5 years ago
- ☆81Updated last year
- ☆30Updated 5 months ago
- The official NaplesPU hardware code repository☆16Updated 5 years ago