Original test vector of RISC-V Vector Extension
☆14Mar 23, 2021Updated 4 years ago
Alternatives and similar repositories for riscv-vector-tests
Users that are interested in riscv-vector-tests are comparing it to the libraries listed below
Sorting:
- ☆12Nov 11, 2015Updated 10 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- AES RoCC Accelerator☆10May 20, 2021Updated 4 years ago
- Unit tests generator for RVV 1.0☆103Nov 11, 2025Updated 3 months ago
- R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point☆17Dec 23, 2025Updated 2 months ago
- ☆15Sep 27, 2022Updated 3 years ago
- RISC-V implementation of the C/C++ Atomic operations library☆22Feb 11, 2019Updated 7 years ago
- RiVEC Bencmark Suite☆128Nov 27, 2024Updated last year
- Implements kernels with RISC-V Vector☆22Mar 24, 2023Updated 2 years ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Nov 26, 2020Updated 5 years ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆54Apr 11, 2020Updated 5 years ago
- ☆27Aug 2, 2021Updated 4 years ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆35Mar 26, 2024Updated last year
- RISCV core RV32I/E.4 threads in a ring architecture☆33Jun 12, 2023Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆34Dec 11, 2025Updated 2 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆34Jun 22, 2024Updated last year
- Semi-private RTL development upstream of OpenCPI - this is *not* the OpenCPI repo!☆25Oct 19, 2016Updated 9 years ago
- MIPS 57条指令五级流水线cpu (verilog实现+详细注释)☆11Jan 11, 2022Updated 4 years ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- TEMPORARY FORK of the riscv-compliance repository☆32Mar 31, 2021Updated 4 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- ☆39Dec 8, 2024Updated last year
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- IEEE 754 single precision floating point library in systemverilog and vhdl☆40Updated this week
- Port of the LLVM compiler infrastructure to the time-predictable processor Patmos☆15Apr 2, 2025Updated 11 months ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- ☆42Feb 3, 2026Updated last month
- ☆43Mar 31, 2025Updated 11 months ago
- A matrix extension proposal for AI applications under RISC-V architecture☆164Feb 11, 2025Updated last year
- Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.☆12Dec 5, 2019Updated 6 years ago
- Fast Matrix Multiplication Implementation in C programming language. This matrix multiplication algorithm is similar to what Numpy uses t…☆41Jun 6, 2021Updated 4 years ago
- ☆12Feb 15, 2024Updated 2 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- ☆11Aug 23, 2023Updated 2 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Oct 31, 2021Updated 4 years ago