msyksphinz-self / riscv-vector-tests
Original test vector of RISC-V Vector Extension
☆11Updated 4 years ago
Alternatives and similar repositories for riscv-vector-tests:
Users that are interested in riscv-vector-tests are comparing it to the libraries listed below
- HLS for Networks-on-Chip☆34Updated 4 years ago
- matrix-coprocessor for RISC-V☆14Updated this week
- ☆33Updated last month
- SystemVerilog Functional Coverage for RISC-V ISA☆27Updated 6 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- RISC-V IOMMU in verilog☆17Updated 2 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 2 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 2 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆39Updated 2 years ago
- ☆25Updated 2 weeks ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆71Updated this week
- Ratatoskr NoC Simulator☆24Updated 4 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated last week
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- Advanced Architecture Labs with CVA6☆57Updated last year
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆34Updated last month
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆55Updated last month
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆30Updated last year
- eyeriss-chisel3☆40Updated 2 years ago
- ☆43Updated 6 years ago
- RISC-V Matrix Specification☆21Updated 4 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 7 months ago
- ☆27Updated 4 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 9 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 4 months ago
- verification of simple axi-based cache☆18Updated 5 years ago