Alternatives and similar repositories for riscv-control-transfer-records:

Users that are interested in riscv-control-transfer-records are comparing it to the libraries listed below

• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆37Updated last year
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆60Updated 3 years ago
• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆12Updated 6 months ago
• riscv-non-isa / iopmp-spec
  This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protectio…
  ☆26Updated this week
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆50Updated last week
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆16Updated 2 weeks ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆29Updated 3 months ago
• michaeljclark / rv8-bench
  rv8 benchmark suite
  ☆19Updated 4 years ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆74Updated last year
• riscv / riscv-cfi
  This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …
  ☆86Updated last month
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆18Updated this week
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆88Updated this week
• dramforever / opensbi-h
  WIP: A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆37Updated 3 weeks ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆36Updated last month
• ccelio / riscv-hpmcounters
  A simple utility for doing RISC-V HPM perf monitoring.
  ☆14Updated 7 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆32Updated 3 years ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆37Updated 2 years ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆37Updated this week
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆38Updated 8 months ago
• riscv-non-isa / riscv-security-model
  RISC-V Security Model
  ☆30Updated last week
• cnrv / RISCV-East-Asia-Biweekly-Sync
  Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.
  ☆23Updated this week
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆46Updated this week
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• ucb-bar / libgloss-htif
  A libgloss replacement for RISC-V that supports HTIF
  ☆28Updated 10 months ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 6 years ago