This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
☆23Mar 10, 2026Updated 2 weeks ago
Alternatives and similar repositories for riscv-control-transfer-records
Users that are interested in riscv-control-transfer-records are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RV32I by cats☆15Sep 4, 2023Updated 2 years ago
- A 3d printed case design for Lichee Pi 4A☆11May 13, 2023Updated 2 years ago
- Vijos: Vijos Isn't Just an Operating System☆10May 31, 2020Updated 5 years ago
- My RV64 CPU (Work in progress)☆19Dec 22, 2022Updated 3 years ago
- CIDR union / subtraction☆14Mar 13, 2026Updated 2 weeks ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- A Rocket-Chip with a Dynamically Randomized LLC☆13Sep 18, 2024Updated last year
- User-mode trap-and-emulate hypervisor for RISC-V☆14Feb 11, 2022Updated 4 years ago
- What if everything is a io_uring?☆17Nov 10, 2022Updated 3 years ago
- [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support☆43Aug 15, 2025Updated 7 months ago
- My DAC '21 work open-sourced.☆14Feb 25, 2021Updated 5 years ago
- Proof-of-concept for I See Dead Micro-Ops transient execution attack☆14Nov 3, 2021Updated 4 years ago
- This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …☆96Mar 20, 2026Updated last week
- ☆12Jul 3, 2018Updated 7 years ago
- ☆38Aug 6, 2022Updated 3 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 4 years ago
- Plagiarism detection tool in Rust (inspired by Stanford Moss)☆54Sep 12, 2025Updated 6 months ago
- Spike with a coherence supported cache model☆14Jul 9, 2024Updated last year
- Implements kernels with RISC-V Vector☆22Mar 24, 2023Updated 3 years ago
- Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)☆16Jan 26, 2020Updated 6 years ago
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 5 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 4 years ago
- 网络学堂 PC 端 App☆21Mar 12, 2026Updated 2 weeks ago
- CoreMark 1.0 ported to WebAssembly☆45Apr 2, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core☆17Jul 20, 2023Updated 2 years ago
- ☆22Nov 12, 2020Updated 5 years ago
- A stack-based language implemented in RISC-V assembly☆17Apr 4, 2024Updated last year
- Dockerfile with Vivado for CI☆27Apr 17, 2020Updated 5 years ago
- Open-Source EDA workshop for RISC-V community☆12Jul 27, 2022Updated 3 years ago
- ☆32Updated this week
- A simple program to make your Linux server act as TCP Transparent Proxy.☆25Mar 7, 2020Updated 6 years ago
- A hardware accelerated IP packet forwarder running on programmable ICs☆15Jan 21, 2023Updated 3 years ago
- RISC-V Nexus Trace TG documentation and reference code☆58Mar 20, 2026Updated last week
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- ☆13May 17, 2016Updated 9 years ago
- SGX protected filesystem demo☆12Jul 28, 2017Updated 8 years ago
- Sail RISC-V model☆682Updated this week
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆14Dec 20, 2016Updated 9 years ago
- A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.☆30May 14, 2020Updated 5 years ago
- The RAS Error-record Register Interface provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting …☆11Mar 20, 2026Updated last week
- Securing Embedded Systems with Return Address Integrity☆15Aug 19, 2024Updated last year