riscv / riscv-control-transfer-recordsLinks

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
21Updated 4 months ago

Alternatives and similar repositories for riscv-control-transfer-records

Users that are interested in riscv-control-transfer-records are comparing it to the libraries listed below

Sorting: