Alternatives and similar repositories for riscv-control-transfer-records

Users that are interested in riscv-control-transfer-records are comparing it to the libraries listed below

• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆13Updated last year
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated last month
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• dramforever / opensbi-h
  [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆41Updated 3 months ago
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆14Updated 3 years ago
• riscv / riscv-cfi
  This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …
  ☆93Updated last week
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆42Updated 2 weeks ago
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆64Updated last week
• OpenRigil / openrigil-rtl
  Open-source RISC-V cryptographic hardware token, RTL repo
  ☆20Updated 3 years ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆22Updated 8 months ago
• Compass-All / Raft
  Hardware-assisted Dynamic Information Flow Tracking for Runtime Protection on RISC-V
  ☆11Updated 2 years ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Updated 3 years ago
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆24Updated last month
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆44Updated this week
• CTSRD-CHERI / garnet
  Amazon F1-inspired Xilinx VCU118 hardware design framework
  ☆12Updated 4 years ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆93Updated 6 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 2 weeks ago
• riscvarchive / riscv-CMOs
  ☆89Updated 3 months ago
• kuczmmar / Runahead
  Running ahead of memory latency - Part II project
  ☆10Updated 2 years ago
• renxida / iseedeaduops-poc
  Proof-of-concept for I See Dead Micro-Ops transient execution attack
  ☆14Updated 4 years ago
• jiegec / kb
  My knowledge base
  ☆73Updated last month
• iscas-tis / chisel-formal-verification
  Formal verification tools for Chisel and RISC-V
  ☆13Updated last year
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆107Updated 2 months ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆35Updated 2 weeks ago
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆119Updated last year
• ccelio / riscv-hpmcounters
  A simple utility for doing RISC-V HPM perf monitoring.
  ☆18Updated 8 years ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 7 years ago