riscv / riscv-control-transfer-recordsLinks
This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
☆21Updated 4 months ago
Alternatives and similar repositories for riscv-control-transfer-records
Users that are interested in riscv-control-transfer-records are comparing it to the libraries listed below
Sorting:
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- Run Rocket Chip on VCU128☆30Updated 7 months ago
- WIP: A fork of OpenSBI, with software-emulated hypervisor extension support☆39Updated 4 months ago
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- A Rocket-Chip with a Dynamically Randomized LLC☆13Updated 9 months ago
- This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…☆54Updated this week
- What if everything is a io_uring?☆16Updated 2 years ago
- The MIPS CPU from previous CQU NSCSCC team and debugged by me running uCore MIPS porting successfully☆9Updated 4 years ago
- An SoC with multiple RISC-V IMA processors.☆19Updated 6 years ago
- A bare-metal application to test specific features of the risc-v hypervisor extension☆40Updated last year
- ☆17Updated 3 years ago
- A hand-written recursive decent Verilog parser.☆11Updated 2 years ago
- CPU micro benchmarks☆58Updated 3 weeks ago
- The 'missing header' for Chisel☆20Updated 3 months ago
- Microarchitecture diagrams of several CPUs☆37Updated this week
- User-mode trap-and-emulate hypervisor for RISC-V☆13Updated 3 years ago
- This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …☆88Updated this week
- Open-source high-performance non-blocking cache☆86Updated last month
- RISC-V architecture concurrency model litmus tests☆81Updated last month
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆19Updated 7 months ago
- Wrappers for open source FPU hardware implementations.☆32Updated last year
- Lower chisel memories to SRAM macros☆12Updated last year
- Open-source RISC-V cryptographic hardware token, RTL repo☆19Updated 2 years ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆37Updated 2 years ago
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆117Updated 8 months ago
- Open-source non-blocking L2 cache☆43Updated this week
- ☆86Updated 3 years ago
- A Symmetric Multiprocessing OS Kernel over RISC-V☆31Updated 3 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Updated 3 years ago