AmbiML / iree-rv32-springbokLinks
☆23Updated 2 years ago
Alternatives and similar repositories for iree-rv32-springbok
Users that are interested in iree-rv32-springbok are comparing it to the libraries listed below
Sorting:
- Chisel RISC-V Vector 1.0 Implementation☆114Updated 2 weeks ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆140Updated this week
- Example for running IREE in a bare-metal Arm environment.☆39Updated 2 months ago
- ☆79Updated last week
- ☆59Updated this week
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆51Updated 2 years ago
- high-performance RTL simulator☆178Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆122Updated last week
- The specification for the FIRRTL language☆61Updated 2 weeks ago
- A tool for synthesizing Verilog programs☆103Updated last month
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated last week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- ☆32Updated this week
- A GPU acceleration flow for RTL simulation with batch stimulus☆114Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 3 months ago
- Simple runtime for Pulp platforms☆49Updated 2 weeks ago
- CGRA framework with vectorization support.☆35Updated last week
- ☆61Updated this week
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆115Updated 5 months ago
- DNN Compiler for Heterogeneous SoCs☆52Updated last week
- Debuggable hardware generator☆70Updated 2 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆109Updated 2 years ago
- Vector Acceleration IP core for RISC-V*☆184Updated 5 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- The multi-core cluster of a PULP system.☆108Updated 2 weeks ago
- A stream to RTL compiler based on MLIR and CIRCT☆15Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆66Updated 11 months ago
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆87Updated 2 weeks ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆42Updated this week
- Testing processors with Random Instruction Generation☆47Updated last week