Twine-Umich / TwineLinks
☆11Updated 3 years ago
Alternatives and similar repositories for Twine
Users that are interested in Twine are comparing it to the libraries listed below
Sorting:
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 4 months ago
- Next generation CGRA generator☆115Updated this week
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆86Updated 3 weeks ago
- ☆15Updated 4 years ago
- A Hardware Pipeline Description Language☆48Updated 3 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated last month
- Floating point modules for CHISEL☆31Updated 11 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- A Rocket-based RISC-V superscalar in-order core☆35Updated 3 weeks ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- Chisel components for FPGA projects☆127Updated 2 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 4 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- A parallel and distributed simulator for thousand-core chips☆26Updated 7 years ago
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆31Updated last year
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated this week
- ☆87Updated 4 months ago
- ☆60Updated this week
- ☆29Updated 8 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆156Updated last year
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆148Updated 2 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆51Updated 2 years ago
- Lipsi: Probably the Smallest Processor in the World☆88Updated last year
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆27Updated 2 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago