Twine-Umich / Twine
☆10Updated 2 years ago
Related projects: ⓘ
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆36Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆45Updated 4 years ago
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆69Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆38Updated 4 years ago
- DASS HLS Compiler☆26Updated 11 months ago
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆29Updated 4 months ago
- Floating point modules for CHISEL☆27Updated 9 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆41Updated 3 years ago
- A hardware synthesis framework with multi-level paradigm☆31Updated last year
- ☆14Updated 3 years ago
- ☆11Updated last year
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆26Updated last year
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆22Updated last year
- ☆22Updated 3 years ago
- A Hardware Pipeline Description Language☆39Updated 10 months ago
- A polyhedral compiler for hardware accelerators☆55Updated last month
- ☆46Updated this week
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆43Updated last year
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆57Updated 2 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆27Updated 10 months ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 3 years ago
- ☆27Updated 5 years ago
- Polyhedral High-Level Synthesis in MLIR☆27Updated last year
- Papers, Posters, Presentations, Documentation...☆18Updated 8 months ago
- Next generation CGRA generator☆104Updated this week
- A Rocket-based RISC-V superscalar in-order core☆26Updated last month
- FPGA acceleration of arbitrary precision floating point computations.☆34Updated 2 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆53Updated 2 weeks ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆17Updated this week
- Chisel library for Unum Type-III Posit Arithmetic☆30Updated 5 months ago