Twine-Umich / Twine
☆10Updated 2 years ago
Alternatives and similar repositories for Twine:
Users that are interested in Twine are comparing it to the libraries listed below
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆70Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated last month
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 4 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- Next generation CGRA generator☆108Updated this week
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Floating point modules for CHISEL☆31Updated 10 years ago
- DASS HLS Compiler☆27Updated last year
- A fault-injection framework using Chisel and FIRRTL☆34Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- A home for Genesis2 sources.☆39Updated last week
- ILA Model Database☆22Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated last week
- A hardware synthesis framework with multi-level paradigm☆36Updated 3 weeks ago
- ☆15Updated last year
- ☆15Updated 3 years ago
- ☆133Updated 2 years ago
- A vector processor implemented in Chisel☆21Updated 10 years ago
- A Hardware Pipeline Description Language☆44Updated last year
- A Rocket-based RISC-V superscalar in-order core☆29Updated 3 months ago
- A polyhedral compiler for hardware accelerators☆55Updated 6 months ago
- ☆77Updated 2 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆30Updated 8 months ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆83Updated 10 months ago
- Chisel library for Unum Type-III Posit Arithmetic☆36Updated 9 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆66Updated 5 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 5 months ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆54Updated last month