Twine-Umich / Twine
☆10Updated 3 years ago
Alternatives and similar repositories for Twine:
Users that are interested in Twine are comparing it to the libraries listed below
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆39Updated 2 weeks ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Next generation CGRA generator☆110Updated this week
- ☆24Updated 4 years ago
- DASS HLS Compiler☆29Updated last year
- ☆28Updated 5 years ago
- A hardware synthesis framework with multi-level paradigm☆38Updated 2 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- ☆15Updated 2 years ago
- ☆15Updated 4 years ago
- A Rocket-based RISC-V superscalar in-order core☆31Updated this week
- Polyhedral High-Level Synthesis in MLIR☆30Updated 2 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆100Updated 5 years ago
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆31Updated 10 months ago
- ☆26Updated 7 years ago
- ☆55Updated this week
- ☆57Updated last year
- A Language for Closed-form High-level ARchitecture Modeling☆20Updated 5 years ago
- Languages, Tools, and Techniques for Accelerator Design☆32Updated 3 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆55Updated last month
- Floating point modules for CHISEL☆31Updated 10 years ago
- Xilinx Modifications to Halide☆12Updated 3 years ago
- A DSL for Systolic Arrays☆78Updated 6 years ago
- A parallel and distributed simulator for thousand-core chips☆24Updated 6 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆23Updated 2 years ago
- A home for Genesis2 sources.☆41Updated 2 weeks ago