Alternatives and similar repositories for RISC-V-TLM

Users that are interested in RISC-V-TLM are comparing it to the libraries listed below

• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆262Updated 6 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆302Updated 2 years ago
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆320Updated 2 months ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆472Updated this week
• riscv-ovpsim / imperas-riscv-tests
  ☆190Updated last year
• sparcians / map
  Modeling Architectural Platform
  ☆212Updated 2 weeks ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆221Updated 5 years ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆180Updated 11 months ago
• machineware-gmbh / vcml
  A modeling library with virtual components for SystemC and TLM simulators
  ☆174Updated this week
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆191Updated this week
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆151Updated 5 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆75Updated last month
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆223Updated 3 weeks ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 7 years ago
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆156Updated 6 months ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆138Updated 3 years ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆394Updated last month
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆130Updated 5 years ago
• RV-BOSC / OpenNoC
  ☆209Updated 5 months ago
• davidepatti / noxim
  Network on Chip Simulator
  ☆292Updated last month
• chipsalliance / Cores-VeeR-EH2
  ☆250Updated 2 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆283Updated last week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆331Updated 11 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆202Updated last year
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆247Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆544Updated last month
• learnwithexamples / learnsystemc
  Learn systemC with examples
  ☆125Updated 2 years ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆262Updated 3 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆183Updated 3 months ago