Alternatives and similar repositories for RISC-V-TLM

Users that are interested in RISC-V-TLM are comparing it to the libraries listed below

• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆254Updated 3 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆292Updated last year
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆299Updated 3 months ago
• sparcians / map
  Modeling Architectural Platform
  ☆200Updated 2 weeks ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆453Updated 3 weeks ago
• riscv-ovpsim / imperas-riscv-tests
  ☆182Updated last year
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 4 years ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆174Updated 8 months ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆180Updated 6 years ago
• learnwithexamples / learnsystemc
  Learn systemC with examples
  ☆119Updated 2 years ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆185Updated this week
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆381Updated last month
• machineware-gmbh / vcml
  A modeling library with virtual components for SystemC and TLM simulators
  ☆164Updated this week
• RV-BOSC / OpenNoC
  ☆184Updated last month
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆142Updated 5 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆72Updated last month
• davidepatti / noxim
  Network on Chip Simulator
  ☆287Updated last month
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆111Updated this week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆197Updated last year
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆207Updated this week
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆206Updated 2 months ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆136Updated 2 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆188Updated 2 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆181Updated 8 months ago
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆153Updated 3 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆525Updated 2 weeks ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆221Updated 3 weeks ago
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆102Updated 6 years ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆120Updated 8 months ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆279Updated 3 months ago