ccelio / SpeckleView external linksLinks
A wrapper for the SPEC CPU2006 benchmark suite.
☆91May 6, 2021Updated 4 years ago
Alternatives and similar repositories for Speckle
Users that are interested in Speckle are comparing it to the libraries listed below
Sorting:
- A simple utility for doing RISC-V HPM perf monitoring.☆18May 8, 2017Updated 8 years ago
- Documentation for the BOOM processor☆47Mar 8, 2017Updated 8 years ago
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated 10 months ago
- The Splash-3 benchmark suite☆45Apr 24, 2023Updated 2 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆238Nov 20, 2024Updated last year
- A detailed michroarchitectural x86 simulator☆62Apr 14, 2017Updated 8 years ago
- Interprocedural Basic Block Code Layout Optimization☆18Jan 17, 2019Updated 7 years ago
- ☆16Nov 28, 2024Updated last year
- A port of the RIPE suite to RISC-V.☆29Oct 10, 2018Updated 7 years ago
- RISC CPU by Icenowy☆12Dec 26, 2018Updated 7 years ago
- Proof-of-concept for I See Dead Micro-Ops transient execution attack☆14Nov 3, 2021Updated 4 years ago
- The artifact for SecSMT paper -- Usenix Security 2022☆31Oct 4, 2022Updated 3 years ago
- An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher☆36Nov 9, 2022Updated 3 years ago
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆59Dec 19, 2023Updated 2 years ago
- Extremely Simple Microbenchmarks☆39May 23, 2018Updated 7 years ago
- Microprobe: Microbenchmark generation framework☆25Feb 5, 2026Updated last week
- A Modified gem5 for Simulating Virtualized Systems☆11Mar 1, 2015Updated 10 years ago
- firrtlator is a FIRRTL C++ library☆23Dec 15, 2016Updated 9 years ago
- ☆64Dec 4, 2022Updated 3 years ago
- chisel tutorial exercises and answers☆743Jan 6, 2022Updated 4 years ago
- Run SPEC CPU2006 on Linux with either an Intel, ARM, or PowerPC processors.☆26Apr 25, 2018Updated 7 years ago
- [WIP] Interval Analysis on LLVM IR☆12Jul 6, 2020Updated 5 years ago
- ☆11Jan 6, 2020Updated 6 years ago
- Code/schematics for a clock using a Panaplex (planar gas discharge) display☆12Dec 1, 2017Updated 8 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Nov 22, 2019Updated 6 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,072Feb 5, 2026Updated last week
- This is a fork of zsim (see https://github.com/s5z/zsim) which integrates the NVMain main memory simulator, adding 3D stacking and non-vo…☆26Jan 15, 2015Updated 11 years ago
- A configurable SRAM generator☆58Aug 19, 2025Updated 5 months ago
- Tests for example Rocket Custom Coprocessors☆75Feb 19, 2020Updated 5 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,138Updated this week
- Base repo of a workable zsim on newer version of Ubuntu, with PIN-2.14 binary (the original zSim no longer works)☆14Nov 20, 2022Updated 3 years ago
- A JavaScript implementation of the Logic Programming System described in section 4.4 of "Structure and Interpretation of Computer Program…☆22Jan 25, 2012Updated 14 years ago
- Data-centric defense mechanism against Spectre attacks. (DAC'19)☆11Nov 6, 2019Updated 6 years ago
- A template for building new projects/platforms using the BOOM core.☆25Jan 14, 2019Updated 7 years ago
- Creating beautiful gem5 simulations☆49Mar 22, 2021Updated 4 years ago
- Fluid Pipelines☆11May 4, 2018Updated 7 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Aug 2, 2019Updated 6 years ago
- New Cache implementation using Gem5☆13Apr 2, 2014Updated 11 years ago
- ☆13Feb 6, 2021Updated 5 years ago