ccelio / Speckle
A wrapper for the SPEC CPU2006 benchmark suite.
☆89Updated 4 years ago
Alternatives and similar repositories for Speckle
Users that are interested in Speckle are comparing it to the libraries listed below
Sorting:
- The gem5-X open source framework (based on the gem5 simulator)☆41Updated last year
- upstream: https://github.com/RALC88/gem5☆31Updated last year
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- RiVEC Bencmark Suite☆114Updated 5 months ago
- Official repository of the Arm Research Starter Kit on System Modeling using gem5☆114Updated last year
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆51Updated 4 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- Joint HPS and ETH Repository to work towards open sourcing Scarab and Ramulator☆77Updated last year
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆71Updated 8 months ago
- gem5 Tips & Tricks☆69Updated 5 years ago
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆133Updated last year
- Support for Rocket Chip on Zynq FPGAs☆40Updated 6 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 2 years ago
- Extremely Simple Microbenchmarks☆33Updated 6 years ago
- ☆91Updated last year
- Creating beautiful gem5 simulations☆49Updated 4 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆151Updated 3 years ago
- The official repository for the gem5 resources sources.☆68Updated 3 weeks ago
- Comment on the rocket-chip source code☆179Updated 6 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆65Updated 10 months ago
- ☆32Updated 5 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆121Updated 5 years ago
- Chisel Learning Journey☆109Updated 2 years ago
- The gem5 Bootcamp 2022 environment. Archived.☆36Updated 10 months ago
- ☆84Updated this week
- A heterogeneous architecture timing model simulator.☆154Updated 5 months ago
- The Sniper Multi-Core Simulator☆126Updated 6 months ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆63Updated 5 years ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆235Updated 2 years ago
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆184Updated 4 years ago