ccelio / Speckle
A wrapper for the SPEC CPU2006 benchmark suite.
☆86Updated 3 years ago
Alternatives and similar repositories for Speckle:
Users that are interested in Speckle are comparing it to the libraries listed below
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆130Updated last year
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆58Updated last year
- Official repository of the Arm Research Starter Kit on System Modeling using gem5☆113Updated last year
- upstream: https://github.com/RALC88/gem5☆31Updated last year
- Comment on the rocket-chip source code☆171Updated 6 years ago
- Extremely Simple Microbenchmarks☆31Updated 6 years ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆61Updated 5 years ago
- RiVEC Bencmark Suite☆110Updated 2 months ago
- gem5 Tips & Tricks☆66Updated 4 years ago
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆72Updated 5 months ago
- Support for Rocket Chip on Zynq FPGAs☆40Updated 5 years ago
- Tests for example Rocket Custom Coprocessors☆69Updated 5 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆46Updated 2 years ago
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆48Updated 3 years ago
- ☆90Updated last year
- Fork of main gem5 repo: https://gem5.googlesource.com/public/gem5/☆21Updated 2 weeks ago
- CVA6 SDK containing RISC-V tools and Buildroot☆61Updated 7 months ago
- A heterogeneous architecture timing model simulator.☆145Updated 2 months ago
- Joint HPS and ETH Repository to work towards open sourcing Scarab and Ramulator☆72Updated 9 months ago
- Heterogeneous simulator for DECADES Project☆31Updated 8 months ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆147Updated 2 years ago
- Creating beautiful gem5 simulations☆47Updated 3 years ago
- RISC-V Torture Test☆179Updated 7 months ago
- ☆30Updated 4 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆84Updated this week
- Documentation for RISC-V Spike☆99Updated 6 years ago
- Championship Value Prediction (CVP) simulator.☆15Updated 4 years ago
- Memory System Microbenchmarks☆62Updated 2 years ago
- Artifact, reproducibility, and testing utilites for gem5☆21Updated 3 years ago