ccelio / SpeckleLinks
A wrapper for the SPEC CPU2006 benchmark suite.
☆91Updated 4 years ago
Alternatives and similar repositories for Speckle
Users that are interested in Speckle are comparing it to the libraries listed below
Sorting:
- Official repository of the Arm Research Starter Kit on System Modeling using gem5☆118Updated 7 months ago
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆143Updated 2 years ago
- ☆33Updated 5 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- RiVEC Bencmark Suite☆127Updated last year
- A heterogeneous architecture timing model simulator.☆174Updated 4 months ago
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆56Updated 4 years ago
- ESESC: A Fast Multicore Simulator☆140Updated 2 months ago
- upstream: https://github.com/RALC88/gem5☆33Updated 2 years ago
- Extremely Simple Microbenchmarks☆39Updated 7 years ago
- Joint HPS and ETH Repository to work towards open sourcing Scarab and Ramulator☆83Updated 4 months ago
- Artifact, reproducibility, and testing utilites for gem5☆23Updated 4 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆64Updated 2 years ago
- gem5 configuration for intel's skylake micro-architecture☆53Updated 4 years ago
- The official repository for the gem5 resources sources.☆80Updated 2 weeks ago
- Creating beautiful gem5 simulations☆49Updated 4 years ago
- DRAMSim2: A cycle accurate DRAM simulator☆294Updated 5 years ago
- gem5 Tips & Tricks☆71Updated 5 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆162Updated 3 years ago
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆76Updated 4 months ago
- Championship Value Prediction (CVP) simulator.☆17Updated 4 years ago
- RISC-V architecture concurrency model litmus tests☆97Updated this week
- The gem5 Bootcamp 2022 environment. Archived.☆36Updated last year
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆68Updated 6 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Comment on the rocket-chip source code☆179Updated 7 years ago
- The MiBench testsuite, extended for use in general embedded environments☆112Updated 13 years ago
- Documentation for RISC-V Spike☆105Updated 7 years ago
- ☆64Updated 3 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago