CTSRD-CHERI / TestRIG
Testing processors with Random Instruction Generation
☆29Updated last month
Related projects ⓘ
Alternatives and complementary repositories for TestRIG
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆35Updated 3 years ago
- HW Design Collateral for Caliptra RoT IP☆75Updated this week
- SCARV: a side-channel hardened RISC-V platform☆24Updated last year
- ☆23Updated 3 years ago
- A Modular Open-Source Hardware Fuzzing Framework☆29Updated 2 years ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆60Updated this week
- Hardware generator debugger☆71Updated 8 months ago
- Fiber-based SystemVerilog Simulator.☆25Updated 2 years ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆13Updated 2 weeks ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 7 years ago
- CoreIR Symbolic Analyzer☆61Updated 4 years ago
- A bare-metal application to test specific features of the risc-v hypervisor extension☆34Updated 10 months ago
- ☆25Updated 9 months ago
- CHERI-RISC-V model written in Sail☆55Updated last month
- RTLCheck☆17Updated 6 years ago
- RISC-V Formal Verification Framework☆107Updated 3 weeks ago
- ☆14Updated 3 months ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆24Updated this week
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆27Updated 6 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆135Updated 2 weeks ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆79Updated this week
- Iodine: Verifying Constant-Time Execution of Hardware☆11Updated 3 years ago
- A formalization of the RVWMO (RISC-V) memory model☆30Updated 2 years ago
- Equivalence checking with Yosys☆30Updated this week
- ILA Model Database☆20Updated 4 years ago
- Integer Multiplier Generator for Verilog☆16Updated last year
- COATCheck☆12Updated 6 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆18Updated this week
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆42Updated 3 weeks ago
- RISC-V architecture concurrency model litmus tests☆70Updated last year