Alternatives and similar repositories for TestRIG

Users that are interested in TestRIG are comparing it to the libraries listed below

• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆38Updated 4 years ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆119Updated 8 months ago
• ymanerka / rtlcheck
  RTLCheck
  ☆24Updated 7 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆36Updated 4 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago
• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆27Updated 2 years ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆81Updated last year
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆101Updated this week
• tdb-alcorn / chisel-formal
  ☆24Updated 4 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated last year
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆152Updated last week
• comsec-group / encarsia
  ☆26Updated 9 months ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆66Updated 6 months ago
• gokhankici / iodine
  Iodine: Verifying Constant-Time Execution of Hardware
  ☆15Updated 4 years ago
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 8 years ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆60Updated last year
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 4 months ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆24Updated 5 years ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆35Updated 2 weeks ago
• MikeCovrado / GettingVerilatorStartedWithUVM
  Simple UVM environment for experimenting with Verilator.
  ☆28Updated 2 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆176Updated 2 weeks ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆38Updated last week
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆23Updated 6 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆54Updated last week
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆28Updated 3 years ago
• CTSRD-CHERI / garnet
  Amazon F1-inspired Xilinx VCU118 hardware design framework
  ☆13Updated 5 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆182Updated 8 months ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆108Updated 3 months ago
• efeslab / hardware-bugbase
  ☆20Updated last year
• daniellustig / coatcheck
  COATCheck
  ☆13Updated 7 years ago