comsec-group / encarsiaLinks
☆26Updated 9 months ago
Alternatives and similar repositories for encarsia
Users that are interested in encarsia are comparing it to the libraries listed below
Sorting:
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆16Updated 6 months ago
- ☆20Updated last year
- A fork of Yosys that integrates the CellIFT pass☆13Updated 5 months ago
- The SoC used for the beta phase of Hack@DAC 2018.☆18Updated 5 years ago
- Code repository for Coppelia tool☆23Updated 5 years ago
- A Modular Open-Source Hardware Fuzzing Framework☆36Updated 4 years ago
- rfuzz: coverage-directed fuzzing for RTL research platform☆112Updated 3 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆59Updated this week
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆23Updated last year
- Testing processors with Random Instruction Generation☆50Updated last month
- Hardware Formal Verification Tool☆83Updated this week
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆68Updated 6 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆114Updated 2 months ago
- ☆19Updated last year
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆27Updated 6 months ago
- ☆17Updated 4 years ago
- BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect☆11Updated last year
- ☆10Updated 4 years ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆24Updated 2 months ago
- Fast TLB simulator for RISC-V systems☆15Updated 6 years ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆27Updated 2 years ago
- Project Repo for the Simulator Independent Coverage Research☆21Updated 2 years ago
- GPU-enabled Hardware Fuzzer using Genetic Algorithm☆19Updated 2 years ago
- ☆18Updated last week
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆16Updated 7 months ago
- RISC-V IOMMU Demo (Linux & Bao)☆23Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆108Updated 3 months ago
- ☆13Updated last year
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year