Alternatives and similar repositories for encarsia

Users that are interested in encarsia are comparing it to the libraries listed below

• iscas-tis / CHA
  ☆19Updated last year
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 2 months ago
• efeslab / hardware-bugbase
  ☆18Updated last year
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆34Updated 3 years ago
• ymanerka / rtlcheck
  RTLCheck
  ☆22Updated 6 years ago
• iscas-tis / ChiRVFormal
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆14Updated 2 months ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆45Updated last month
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 4 years ago
• skmuduli92 / HyperFuzzer
  ☆16Updated 4 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated 2 weeks ago
• mit-plv / hemiola
  A Coq framework to support structural design and proof of hardware cache-coherence protocols
  ☆14Updated 3 years ago
• epfl-vlsc / parendi
  Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU
  ☆23Updated last year
• CTSRD-CHERI / garnet
  Amazon F1-inspired Xilinx VCU118 hardware design framework
  ☆12Updated 4 years ago
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆31Updated last week
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 3 years ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆28Updated 4 months ago
• euphoric-hardware / rtl-simulation-reading
  ☆17Updated 2 months ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆37Updated 3 months ago
• MikeCovrado / GettingVerilatorStartedWithUVM
  Simple UVM environment for experimenting with Verilator.
  ☆23Updated 3 months ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆45Updated last month
• sterin / super-prove-build
  ☆13Updated 4 years ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆30Updated this week
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆35Updated 3 months ago
• sparcians / stf_spec
  An open-source Simulation Trace Format specification
  ☆14Updated 3 weeks ago
• CMU-SAFARI / Pythia-HDL
  Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …
  ☆17Updated 3 years ago
• comsec-group / mucfi
  Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…
  ☆14Updated 2 months ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆40Updated last month
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆31Updated this week
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆55Updated last month