☆28Mar 31, 2025Updated 11 months ago
Alternatives and similar repositories for encarsia
Users that are interested in encarsia are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆16Feb 12, 2026Updated last month
- ☆13Feb 14, 2026Updated last month
- Project Repo for the Simulator Independent Coverage Research☆21Feb 28, 2023Updated 3 years ago
- ☆25Mar 1, 2023Updated 3 years ago
- ☆13Jun 12, 2024Updated last year
- Code repository for Coppelia tool☆23Nov 12, 2020Updated 5 years ago
- Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation☆49Apr 22, 2025Updated 11 months ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆19Mar 4, 2026Updated 2 weeks ago
- ☆35Aug 7, 2025Updated 7 months ago
- Hardware Formal Verification Tool☆90Mar 14, 2026Updated last week
- Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)☆139Aug 30, 2024Updated last year
- ☆19Jul 12, 2024Updated last year
- Fuzz everything! Now let's fuzz chip!☆35Feb 11, 2026Updated last month
- Hardcaml Verification Tools☆15Jan 15, 2026Updated 2 months ago
- SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs (ICCAD 2023)☆23Dec 5, 2024Updated last year
- ☆25Dec 4, 2025Updated 3 months ago
- ☆14May 24, 2025Updated 9 months ago
- A CPU fuzzer designed for diverse test case generation and execution.☆101Updated this week
- ☆18Jul 11, 2021Updated 4 years ago
- ☆10Jun 11, 2018Updated 7 years ago
- ☆20Jun 12, 2024Updated last year
- work in progress, playing around with btor2 in rust☆12Feb 24, 2026Updated 3 weeks ago
- Analyze experimental data with Programming by Navigation☆17Mar 8, 2026Updated 2 weeks ago
- GPU-enabled Hardware Fuzzer using Genetic Algorithm☆20Jul 12, 2023Updated 2 years ago
- The SoC used for the beta phase of Hack@DAC 2018.☆18May 14, 2020Updated 5 years ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- Papers, Posters, Presentations, Documentation...☆19Jan 9, 2024Updated 2 years ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Oct 9, 2021Updated 4 years ago
- ☆35Mar 17, 2026Updated last week
- design and verification of asynchronous circuits☆44Feb 27, 2026Updated 3 weeks ago
- ☆19Jan 2, 2026Updated 2 months ago
- LEC - Logic Equivalence Checking - Formal Verification☆37Updated this week
- A fork of Yosys that integrates the CellIFT pass☆13Jul 23, 2025Updated 8 months ago
- GuidedSampler: Coverage-guided Sampling of SMT Solutions☆15Jul 9, 2025Updated 8 months ago
- 21st century electronic design automation tools, written in Rust.☆36Updated this week
- ☆37Jun 19, 2019Updated 6 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Nov 20, 2024Updated last year
- The HW-CBMC and EBMC Model Checkers for Verilog☆103Updated this week
- Open-source AI acceleration on FPGA: from ONNX to RTL☆49Updated this week