Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
☆213Feb 8, 2026Updated last month
Alternatives and similar repositories for riscv-perf-model
Users that are interested in riscv-perf-model are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Modeling Architectural Platform☆220Updated this week
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Mar 13, 2026Updated last week
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Nov 20, 2024Updated last year
- ☆197Dec 14, 2023Updated 2 years ago
- The University of Bristol HPC Simulation Engine☆106Aug 30, 2025Updated 6 months ago
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 2 years ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆146Jan 27, 2026Updated last month
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆346Mar 9, 2026Updated 2 weeks ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆132Mar 14, 2026Updated last week
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 6 months ago
- ☆81Mar 10, 2026Updated 2 weeks ago
- ☆152Oct 6, 2023Updated 2 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆49Feb 11, 2026Updated last month
- Instruction Set Generator initially contributed by Futurewei☆307Oct 17, 2023Updated 2 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆165May 1, 2022Updated 3 years ago
- CV32E40X Design-Verification environment☆16Mar 25, 2024Updated last year
- Spike, a RISC-V ISA Simulator☆3,045Updated this week
- ☆22Nov 3, 2025Updated 4 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆32Mar 4, 2026Updated 2 weeks ago
- RISC-V SystemC-TLM simulator☆346Feb 20, 2026Updated last month
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆500Updated this week
- ☆88Mar 17, 2026Updated last week
- RISC-V Architecture Profiles☆177Mar 13, 2026Updated last week
- An open-source Simulation Trace Format specification☆15Nov 12, 2025Updated 4 months ago
- diablo is an Out-Of-Order 64-bit RISC-V processor.☆16Sep 1, 2023Updated 2 years ago
- Sail RISC-V model☆679Mar 17, 2026Updated last week
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆456Aug 3, 2024Updated last year
- RISC-V Opcodes☆842Mar 14, 2026Updated last week
- ☆134Updated this week
- An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM☆16Mar 25, 2025Updated 11 months ago
- ☆665Updated this week
- SystemC/TLM-2.0 Co-simulation framework☆274May 21, 2025Updated 10 months ago
- The official repository for the gem5 computer-system architecture simulator.☆2,527Updated this week
- ☆89Aug 26, 2025Updated 6 months ago
- The multi-core cluster of a PULP system.☆113Mar 12, 2026Updated last week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,111Mar 11, 2026Updated 2 weeks ago
- RISC-V Security Model☆34Updated this week
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆37Updated this week
- ☆25Dec 4, 2025Updated 3 months ago