Alternatives and similar repositories for riscv-perf-model:

Users that are interested in riscv-perf-model are comparing it to the libraries listed below

• sparcians / map
  Modeling Architectural Platform
  ☆180Updated last week
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆113Updated 3 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆169Updated last year
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆274Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆223Updated 4 months ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆238Updated 4 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆186Updated 8 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆79Updated this week
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆250Updated this week
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆63Updated 9 months ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆150Updated 2 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆150Updated last year
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆186Updated last week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆137Updated 2 weeks ago
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆172Updated this week
• riscv / riscv-CMOs
  ☆85Updated 2 years ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆132Updated last month
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆412Updated this week
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆174Updated 6 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆129Updated 2 years ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆109Updated last week
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆174Updated 3 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆99Updated this week
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆182Updated this week
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆158Updated 2 months ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆101Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆68Updated last week
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆88Updated this week
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆160Updated 3 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆132Updated 5 years ago