Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
☆223May 29, 2026Updated 4 months ago
Alternatives and similar repositories for riscv-perf-model
Users that are interested in riscv-perf-model are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Modeling Architectural Platform☆231Updated this week
- RISC-V RV64GC emulator designed for RTL co-simulation☆244Nov 20, 2024Updated last year
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆69Aug 18, 2026Updated last month
- ☆203Dec 14, 2023Updated 2 years ago
- The University of Bristol HPC Simulation Engine☆110Jun 17, 2026Updated 3 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆140Oct 2, 2026Updated last week
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 3 years ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆405Oct 2, 2026Updated last week
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆20Aug 14, 2026Updated last month
- ☆97Updated this week
- ☆92Updated this week
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆154Aug 14, 2026Updated last month
- ☆159Oct 6, 2023Updated 3 years ago
- Instruction Set Generator initially contributed by Futurewei☆317Oct 17, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆170May 1, 2022Updated 4 years ago
- CV32E40X Design-Verification environment☆19Jun 2, 2026Updated 4 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆36May 17, 2026Updated 4 months ago
- Spike, a RISC-V ISA Simulator☆3,247Updated this week
- RISC-V SystemC-TLM simulator☆361Feb 20, 2026Updated 7 months ago
- ☆22Nov 3, 2025Updated 11 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆552Updated this week
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆45Updated this week
- An open-source Simulation Trace Format specification☆17Jun 4, 2026Updated 4 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- SystemC/TLM-2.0 Co-simulation framework☆310Jun 26, 2026Updated 3 months ago
- RISC-V Architecture Profiles☆192Jul 21, 2026Updated 2 months ago
- diablo is an Out-Of-Order 64-bit RISC-V processor.☆17Jun 30, 2026Updated 3 months ago
- Sail RISC-V model☆779Updated this week
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆518Aug 3, 2024Updated 2 years ago
- An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM☆17Aug 30, 2026Updated last month
- RISC-V Opcodes☆884Sep 18, 2026Updated 3 weeks ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆60Updated this week
- ☆163Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully imp…☆798Updated this week
- The official repository for the gem5 computer-system architecture simulator.☆2,866Updated this week
- The multi-core cluster of a PULP system.☆119Oct 5, 2026Updated last week
- ☆90Aug 26, 2025Updated last year
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆38Jun 21, 2023Updated 3 years ago
- educational microarchitectures for risc-v isa☆759Sep 1, 2025Updated last year
- RISC-V Security Model☆39Oct 5, 2026Updated last week