Alternatives and similar repositories for riscv-perf-model

Users that are interested in riscv-perf-model are comparing it to the libraries listed below

• sparcians / map
  Modeling Architectural Platform
  ☆202Updated 3 weeks ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆90Updated 2 weeks ago
• riscv-ovpsim / imperas-riscv-tests
  ☆187Updated last year
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆302Updated 4 months ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆74Updated 2 months ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆255Updated 3 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆293Updated last year
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆103Updated 6 years ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆121Updated 9 months ago
• machineware-gmbh / vcml
  A modeling library with virtual components for SystemC and TLM simulators
  ☆167Updated this week
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆320Updated 8 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆210Updated 3 weeks ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 9 months ago
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆53Updated 4 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆196Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆90Updated 3 weeks ago
• toddmaustin / bringup-bench
  Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …
  ☆194Updated 2 weeks ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆224Updated last month
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆152Updated 7 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆144Updated 5 years ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆461Updated last month
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆183Updated 4 months ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆126Updated 4 years ago
• OpenXiangShan / GEM5
  ☆99Updated this week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆117Updated last week
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆112Updated 3 months ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆137Updated 2 years ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆177Updated 9 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆129Updated this week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago