riscv-software-src / riscv-perf-modelLinks
Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
☆183Updated this week
Alternatives and similar repositories for riscv-perf-model
Users that are interested in riscv-perf-model are comparing it to the libraries listed below
Sorting:
- Modeling Architectural Platform☆197Updated this week
- Unit tests generator for RVV 1.0☆89Updated 3 weeks ago
- ☆182Updated last year
- RiVEC Bencmark Suite☆118Updated 8 months ago
- Instruction Set Generator initially contributed by Futurewei☆290Updated last year
- SystemC/TLM-2.0 Co-simulation framework☆252Updated 2 months ago
- RISC-V Torture Test☆195Updated last year
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆294Updated 2 months ago
- Documentation for RISC-V Spike☆102Updated 6 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆150Updated 5 months ago
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆53Updated 4 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆71Updated last month
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 8 months ago
- RISC-V SystemC-TLM simulator☆314Updated 7 months ago
- Wrapper for Rocket-Chip on FPGAs☆135Updated 2 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆155Updated 3 years ago
- RISC-V IOMMU Specification☆125Updated this week
- ☆93Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆207Updated 2 months ago
- RISC-V Virtual Prototype☆172Updated 7 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆448Updated last week
- A Fast, Low-Overhead On-chip Network☆220Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated 2 weeks ago
- Comment on the rocket-chip source code☆180Updated 6 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆113Updated last week
- Verilog Configurable Cache☆180Updated 8 months ago
- ☆26Updated 8 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆263Updated last month
- Ariane is a 6-stage RISC-V CPU☆141Updated 5 years ago
- Vector Acceleration IP core for RISC-V*☆181Updated 2 months ago