riscv-software-src / riscv-perf-modelLinks
Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
☆189Updated last week
Alternatives and similar repositories for riscv-perf-model
Users that are interested in riscv-perf-model are comparing it to the libraries listed below
Sorting:
- Modeling Architectural Platform☆211Updated this week
- ☆190Updated last year
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆309Updated last month
- Unit tests generator for RVV 1.0☆92Updated last month
- Documentation for RISC-V Spike☆106Updated 7 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆74Updated last week
- RiVEC Bencmark Suite☆122Updated 11 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆233Updated 11 months ago
- SystemC/TLM-2.0 Co-simulation framework☆256Updated 5 months ago
- RISC-V SystemC-TLM simulator☆327Updated 10 months ago
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆55Updated 4 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆159Updated 3 years ago
- Instruction Set Generator initially contributed by Futurewei☆295Updated 2 years ago
- ☆106Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆215Updated 2 months ago
- Comment on the rocket-chip source code☆179Updated 7 years ago
- Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …☆216Updated last week
- RISC-V Torture Test☆200Updated last year
- A Fast, Low-Overhead On-chip Network☆231Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆92Updated 2 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆466Updated 2 months ago
- A matrix extension proposal for AI applications under RISC-V architecture☆153Updated 8 months ago
- RISC-V IOMMU Specification☆137Updated this week
- A modeling library with virtual components for SystemC and TLM simulators☆169Updated this week
- ☆28Updated 9 years ago
- Ariane is a 6-stage RISC-V CPU☆149Updated 5 years ago
- Vector Acceleration IP core for RISC-V*☆184Updated 5 months ago
- Championship Branch Prediction 2025☆59Updated 5 months ago
- RISC-V Virtual Prototype☆179Updated 10 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆122Updated 2 weeks ago