sparcians / map
Modeling Architectural Platform
☆187Updated this week
Alternatives and similar repositories for map:
Users that are interested in map are comparing it to the libraries listed below
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆165Updated 2 weeks ago
- A Chisel RTL generator for network-on-chip interconnects☆195Updated last month
- RiVEC Bencmark Suite☆114Updated 5 months ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆153Updated last year
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆264Updated last month
- ☆173Updated last year
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆422Updated 2 weeks ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 5 months ago
- RISC-V Torture Test☆193Updated 9 months ago
- Instruction Set Generator initially contributed by Futurewei☆279Updated last year
- Unit tests generator for RVV 1.0☆83Updated last month
- RISC-V SystemC-TLM simulator☆303Updated 4 months ago
- Wrapper for Rocket-Chip on FPGAs☆132Updated 2 years ago
- SystemC/TLM-2.0 Co-simulation framework☆240Updated 6 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆252Updated this week
- A dynamic verification library for Chisel.☆148Updated 5 months ago
- RISC-V Virtual Prototype☆167Updated 4 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆267Updated last week
- Vector Acceleration IP core for RISC-V*☆177Updated 2 weeks ago
- A matrix extension proposal for AI applications under RISC-V architecture☆139Updated 2 months ago
- A Fast, Low-Overhead On-chip Network☆200Updated last week
- CVA6 SDK containing RISC-V tools and Buildroot☆65Updated 10 months ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆151Updated 3 years ago
- Verilog Configurable Cache☆178Updated 5 months ago
- Documentation for RISC-V Spike☆100Updated 6 years ago
- Chisel RISC-V Vector 1.0 Implementation☆96Updated this week
- Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …☆326Updated last month
- Vector processor for RISC-V vector ISA☆117Updated 4 years ago
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆365Updated 9 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year