sparcians / mapLinks
Modeling Architectural Platform
☆206Updated this week
Alternatives and similar repositories for map
Users that are interested in map are comparing it to the libraries listed below
Sorting:
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆189Updated 2 weeks ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆306Updated last week
- Unit tests generator for RVV 1.0☆92Updated last week
- A Chisel RTL generator for network-on-chip interconnects☆211Updated last month
- RiVEC Bencmark Suite☆123Updated 10 months ago
- RISC-V SystemC-TLM simulator☆325Updated 9 months ago
- SystemC/TLM-2.0 Co-simulation framework☆256Updated 4 months ago
- ☆189Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆232Updated 10 months ago
- Vector Acceleration IP core for RISC-V*☆183Updated 4 months ago
- A matrix extension proposal for AI applications under RISC-V architecture☆152Updated 7 months ago
- A Fast, Low-Overhead On-chip Network☆228Updated this week
- CVA6 SDK containing RISC-V tools and Buildroot☆74Updated 3 months ago
- Instruction Set Generator initially contributed by Futurewei☆295Updated last year
- A modeling library with virtual components for SystemC and TLM simulators☆168Updated this week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆462Updated 2 months ago
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆54Updated 4 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆282Updated 2 weeks ago
- Comment on the rocket-chip source code☆180Updated 6 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆90Updated last month
- RISC-V Torture Test☆197Updated last year
- A dynamic verification library for Chisel.☆155Updated 10 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Chisel RISC-V Vector 1.0 Implementation☆112Updated last month
- ☆103Updated this week
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆117Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆266Updated last week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆155Updated last year
- Verilog Configurable Cache☆183Updated 10 months ago
- Vector processor for RISC-V vector ISA☆128Updated 4 years ago