Alternatives and similar repositories for marss-riscv:

Users that are interested in marss-riscv are comparing it to the libraries listed below

• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆226Updated 5 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆192Updated 9 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆279Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆173Updated last year
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆113Updated last week
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆156Updated 4 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆174Updated 9 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆252Updated this week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆231Updated 6 months ago
• SpinalHDL / NaxRiscv
  ☆283Updated last month
• riscv / riscv-CMOs
  ☆86Updated 2 years ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆223Updated last year
• riscvarchive / riscv-code-size-reduction
  ☆150Updated last year
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆135Updated 5 years ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆162Updated 3 months ago
• ucb-bar / berkeley-hardfloat
  ☆321Updated 7 months ago
• sparcians / map
  Modeling Architectural Platform
  ☆187Updated this week
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆114Updated 5 months ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆165Updated 2 weeks ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆183Updated last week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆250Updated 2 weeks ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆210Updated last year
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆65Updated 10 months ago
• toddmaustin / bringup-bench
  Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …
  ☆169Updated 2 weeks ago
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆100Updated 6 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆324Updated 10 months ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆167Updated 4 months ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆240Updated 6 months ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆77Updated last year
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆210Updated 3 weeks ago