Alternatives and similar repositories for marss-riscv

Users that are interested in marss-riscv are comparing it to the libraries listed below

• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆235Updated 11 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆202Updated last year
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆164Updated 5 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 6 months ago
• riscvarchive / riscv-CMOs
  ☆89Updated 2 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆189Updated last year
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆298Updated 2 years ago
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• SpinalHDL / NaxRiscv
  ☆301Updated 2 weeks ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆226Updated last year
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆192Updated last week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆273Updated last month
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆139Updated this week
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆123Updated 11 months ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆179Updated 11 months ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆215Updated last year
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆190Updated this week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆245Updated last year
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆195Updated last month
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆151Updated last week
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆75Updated 3 weeks ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆102Updated 4 years ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆91Updated 5 months ago
• toddmaustin / bringup-bench
  Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …
  ☆216Updated 2 weeks ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆151Updated 2 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆123Updated last week
• sparcians / map
  Modeling Architectural Platform
  ☆211Updated 2 weeks ago
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆106Updated 7 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆106Updated last month
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆55Updated 4 years ago