TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
☆165May 1, 2022Updated 3 years ago
Alternatives and similar repositories for marss-riscv
Users that are interested in marss-riscv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Nov 20, 2024Updated last year
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated last month
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆64Mar 13, 2026Updated last week
- RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆54Apr 11, 2020Updated 5 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆228Aug 25, 2020Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆213Feb 8, 2026Updated last month
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆456Aug 3, 2024Updated last year
- RISC-V SystemC-TLM simulator☆346Feb 20, 2026Updated last month
- RISC-V SST CPU Component☆24Jan 23, 2026Updated 2 months ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆132Mar 14, 2026Updated last week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆970Nov 15, 2024Updated last year
- Modeling Architectural Platform☆220Mar 18, 2026Updated last week
- A simple utility for doing RISC-V HPM perf monitoring.☆18May 8, 2017Updated 8 years ago
- An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM☆16Mar 25, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- SystemVerilog Functional Coverage for RISC-V ISA☆34Dec 11, 2025Updated 3 months ago
- Tweaks to Fabrice Bellard's TinyEMU☆150Oct 14, 2023Updated 2 years ago
- Open-source non-blocking L2 cache☆55Updated this week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,157Feb 21, 2026Updated last month
- Sail RISC-V model☆682Updated this week
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆238Jan 14, 2026Updated 2 months ago
- ☆665Updated this week
- TinyEMU (previously known as RISCVEMU) is a small emulator emulating 128 bit RISC-V and x86 machines, written by Fabrice Bellard☆17Nov 15, 2018Updated 7 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆110Sep 18, 2021Updated 4 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆29Oct 20, 2019Updated 6 years ago
- 32-bit Superscalar RISC-V CPU☆1,197Sep 18, 2021Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 8 months ago
- A heterogeneous architecture timing model simulator.☆175Updated this week
- ☆134Updated this week
- RISC-V CPU Core☆417Jun 24, 2025Updated 9 months ago
- SystemC/TLM-2.0 Co-simulation framework☆274May 21, 2025Updated 10 months ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆377Oct 19, 2023Updated 2 years ago
- Random instruction generator for RISC-V processor verification☆1,265Mar 5, 2026Updated 3 weeks ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Simple RISC-V 3-stage Pipeline in Chisel☆604Aug 9, 2024Updated last year
- RISC-V Virtual Prototype☆187Dec 13, 2024Updated last year
- Semi-private RTL development upstream of OpenCPI - this is *not* the OpenCPI repo!☆25Oct 19, 2016Updated 9 years ago
- VeeR EH1 core☆931May 29, 2023Updated 2 years ago
- ☆197Dec 14, 2023Updated 2 years ago
- Public release☆58Sep 3, 2019Updated 6 years ago
- ☆38Oct 21, 2025Updated 5 months ago