Advanced Interface Bus (AIB) die-to-die hardware open source
☆151Sep 23, 2024Updated 2 years ago
Alternatives and similar repositories for aib-phy-hardware
Users that are interested in aib-phy-hardware are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Home of the Advanced Interface Bus (AIB) specification.☆65Aug 30, 2022Updated 4 years ago
- ☆69Jan 7, 2023Updated 3 years ago
- ☆34Feb 20, 2024Updated 2 years ago
- AIB Generator: Analog hardware compiler for AIB PHY☆41Aug 22, 2020Updated 6 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆31Jan 25, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- An open-source UCIe implementation☆139Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆305Updated this week
- pulp_soc is the core building component of PULP based SoCs☆86Jul 17, 2026Updated 3 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆691Updated this week
- ☆52Jun 1, 2021Updated 5 years ago
- OmniXtend cache coherence protocol☆85Jun 10, 2025Updated last year
- OpenSoC Fabric - A Network-On-Chip Generator☆179Jun 18, 2020Updated 6 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,741Updated this week
- An open-source UCIe implementation developed at UC Berkeley.☆21Jul 8, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆329Aug 7, 2026Updated 2 months ago
- Small footprint and configurable DRAM core☆568Updated this week
- Verilog Configurable Cache☆197Sep 21, 2026Updated last month
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Jan 6, 2022Updated 4 years ago
- ☆27Aug 2, 2021Updated 5 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆148Jul 22, 2021Updated 5 years ago
- A Linux-capable RISC-V multicore for and by the world☆840Updated this week
- A toolchain for rapid design space exploration of chiplet architectures☆93Jul 25, 2025Updated last year
- The OpenPiton Platform☆838Updated this week
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- VeeR EH1 core☆972Jul 16, 2026Updated 3 months ago
- ☆16Jul 16, 2026Updated 3 months ago
- An open-source static random access memory (SRAM) compiler.☆1,169Updated this week
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆159Mar 19, 2018Updated 8 years ago
- ☆90Jun 27, 2022Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆58May 10, 2021Updated 5 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆269Updated this week
- ☆25Aug 9, 2022Updated 4 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Oct 5, 2017Updated 9 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,317Updated this week
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- Demo SoC for SiliconCompiler.☆64Jul 2, 2026Updated 3 months ago
- Small footprint and configurable PCIe core☆740Updated this week
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,145Updated this week
- Wishbone SATA Controller☆28Sep 17, 2026Updated last month
- The source code that empowers OpenROAD Cloud☆15Jun 29, 2020Updated 6 years ago