chipsalliance / aib-phy-hardwareLinks
Advanced Interface Bus (AIB) die-to-die hardware open source
☆138Updated 9 months ago
Alternatives and similar repositories for aib-phy-hardware
Users that are interested in aib-phy-hardware are comparing it to the libraries listed below
Sorting:
- OpenSoC Fabric - A Network-On-Chip Generator☆171Updated 5 years ago
- ☆87Updated 4 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆170Updated 7 months ago
- Network on Chip Implementation written in SytemVerilog☆185Updated 2 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆275Updated 2 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆284Updated 2 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆137Updated 3 weeks ago
- Tile based architecture designed for computing efficiency, scalability and generality☆262Updated last month
- ☆66Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆169Updated 3 weeks ago
- Verilog Configurable Cache☆179Updated 7 months ago
- Open-source FPGA research and prototyping framework.☆208Updated 11 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated this week
- Home of the Advanced Interface Bus (AIB) specification.☆54Updated 2 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- A Fast, Low-Overhead On-chip Network☆215Updated this week
- AXI Adapter(s) for RISC-V Atomic Operations☆65Updated 2 months ago
- Generic Register Interface (contains various adapters)☆123Updated last month
- RISC-V Verification Interface☆97Updated last month
- A dynamic verification library for Chisel.☆152Updated 8 months ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆180Updated 5 years ago
- VeeR EL2 Core☆292Updated 2 weeks ago
- Build Customized FPGA Implementations for Vivado☆328Updated last week
- Standard Cell Library based Memory Compiler using FF/Latch cells☆151Updated last week
- Provides dot visualizations of chisel/firrtl circuits☆120Updated 2 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆71Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 7 months ago
- Chisel components for FPGA projects☆125Updated last year
- ☆181Updated last year
- PCI express simulation framework for Cocotb☆168Updated 2 months ago