chipsalliance / aib-phy-hardwareLinks
Advanced Interface Bus (AIB) die-to-die hardware open source
☆142Updated last year
Alternatives and similar repositories for aib-phy-hardware
Users that are interested in aib-phy-hardware are comparing it to the libraries listed below
Sorting:
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆181Updated last year
- ☆97Updated 3 months ago
- Network on Chip Implementation written in SytemVerilog☆194Updated 3 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated this week
- VeeR EL2 Core☆303Updated this week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆302Updated last month
- ☆247Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆187Updated 2 months ago
- Open-source FPGA research and prototyping framework.☆210Updated last year
- OpenSoC Fabric - A Network-On-Chip Generator☆174Updated 5 years ago
- A Fast, Low-Overhead On-chip Network☆239Updated last week
- Home of the Advanced Interface Bus (AIB) specification.☆56Updated 3 years ago
- Basic floating-point components for RISC-V processors☆67Updated 5 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆274Updated last month
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆286Updated 3 weeks ago
- Build Customized FPGA Implementations for Vivado☆344Updated this week
- ☆67Updated 2 years ago
- RISC-V System on Chip Template☆159Updated 3 months ago
- Fabric generator and CAD tools.☆206Updated this week
- This is a tutorial on standard digital design flow☆79Updated 4 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆274Updated last week
- Generic Register Interface (contains various adapters)☆133Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 11 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- A dynamic verification library for Chisel.☆158Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 weeks ago
- An Open-Source Design and Verification Environment for RISC-V☆85Updated 4 years ago
- RISC-V Virtual Prototype☆180Updated 11 months ago