Advanced Interface Bus (AIB) die-to-die hardware open source
☆149Sep 23, 2024Updated last year
Alternatives and similar repositories for aib-phy-hardware
Users that are interested in aib-phy-hardware are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆69Jan 7, 2023Updated 3 years ago
- Home of the Advanced Interface Bus (AIB) specification.☆60Aug 30, 2022Updated 3 years ago
- ☆29Feb 20, 2024Updated 2 years ago
- AIB Generator: Analog hardware compiler for AIB PHY☆39Aug 22, 2020Updated 5 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆30Jan 25, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆48Jun 1, 2021Updated 4 years ago
- OmniXtend cache coherence protocol☆85Jun 10, 2025Updated 11 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆290Apr 30, 2026Updated 3 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,581Updated this week
- ☆15Jul 28, 2022Updated 3 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆664May 11, 2026Updated last week
- pulp_soc is the core building component of PULP based SoCs☆84Mar 10, 2025Updated last year
- ☆27Aug 2, 2021Updated 4 years ago
- An open-source UCIe implementation☆103May 8, 2026Updated last week
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- ☆25Aug 9, 2022Updated 3 years ago
- Wishbone SATA Controller☆25Oct 16, 2025Updated 7 months ago
- BookSim 2.0☆424Jun 24, 2024Updated last year
- Small footprint and configurable DRAM core☆502May 12, 2026Updated last week
- ☆14Feb 24, 2025Updated last year
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Oct 5, 2017Updated 8 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆36Apr 9, 2026Updated last month
- Demo SoC for SiliconCompiler.☆63Mar 29, 2026Updated last month
- VeeR EH1 core☆942May 29, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verilog Configurable Cache☆198Updated this week
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆148Mar 19, 2018Updated 8 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- A Linux-capable RISC-V multicore for and by the world☆803Apr 24, 2026Updated 3 weeks ago
- OpenSoC Fabric - A Network-On-Chip Generator☆178Jun 18, 2020Updated 5 years ago
- Papers, Posters, Presentations, Documentation...☆20Jan 9, 2024Updated 2 years ago
- Small footprint and configurable PCIe core☆695Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,875May 7, 2026Updated 2 weeks ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A toolchain for rapid design space exploration of chiplet architectures☆81Jul 25, 2025Updated 9 months ago
- An open-source static random access memory (SRAM) compiler.☆1,060Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆980Nov 15, 2024Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆128Jul 22, 2021Updated 4 years ago
- Generic Register Interface (contains various adapters)☆140Feb 24, 2026Updated 2 months ago
- A Fast, Low-Overhead On-chip Network☆294May 12, 2026Updated last week
- Common SystemVerilog components☆747May 7, 2026Updated 2 weeks ago