chipsalliance / aib-phy-hardwareLinks
Advanced Interface Bus (AIB) die-to-die hardware open source
☆140Updated 11 months ago
Alternatives and similar repositories for aib-phy-hardware
Users that are interested in aib-phy-hardware are comparing it to the libraries listed below
Sorting:
- ☆91Updated last week
- Network on Chip Implementation written in SytemVerilog☆189Updated 3 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆290Updated 3 months ago
- A Fast, Low-Overhead On-chip Network☆221Updated last month
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆176Updated last week
- Generic Register Interface (contains various adapters)☆126Updated 3 weeks ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆174Updated 9 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆73Updated last year
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆139Updated last month
- Standard Cell Library based Memory Compiler using FF/Latch cells☆155Updated last month
- Tile based architecture designed for computing efficiency, scalability and generality☆263Updated 2 months ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- VeeR EL2 Core☆296Updated this week
- Open-source FPGA research and prototyping framework.☆208Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- RISC-V Verification Interface☆101Updated 2 months ago
- ☆67Updated 2 years ago
- ☆244Updated 2 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆172Updated 5 years ago
- Verilog Configurable Cache☆181Updated 8 months ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 5 months ago
- Vector processor for RISC-V vector ISA☆126Updated 4 years ago
- ☆64Updated 4 years ago
- A dynamic verification library for Chisel.☆155Updated 9 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆279Updated 4 months ago
- Ariane is a 6-stage RISC-V CPU☆143Updated 5 years ago
- Home of the Advanced Interface Bus (AIB) specification.☆54Updated 3 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- Basic RISC-V Test SoC☆140Updated 6 years ago