Alternatives and similar repositories for aib-phy-hardware:

Users that are interested in aib-phy-hardware are comparing it to the libraries listed below

• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆172Updated 2 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆166Updated 5 months ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆85Updated last month
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆194Updated last month
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆266Updated 5 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆145Updated last month
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆274Updated last week
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆277Updated this week
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆197Updated this week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆250Updated last month
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆234Updated 11 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆113Updated 7 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆89Updated 2 months ago
• chipsalliance / AIB-specification
  Home of the Advanced Interface Bus (AIB) specification.
  ☆52Updated 2 years ago
• intel / aib-phy-hardware
  ☆66Updated 2 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆144Updated 10 months ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆130Updated last year
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆148Updated 5 months ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆242Updated 6 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆156Updated 4 years ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆313Updated last week
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated last month
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆147Updated 5 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆133Updated last month
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆249Updated 2 months ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆64Updated 10 months ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆61Updated 2 weeks ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆74Updated 7 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆175Updated 4 months ago