google / chiplets-cost-modelLinks
☆24Updated 3 years ago
Alternatives and similar repositories for chiplets-cost-model
Users that are interested in chiplets-cost-model are comparing it to the libraries listed below
Sorting:
- SRAM build space for SKY130 provided by SkyWater.☆24Updated 4 years ago
- An Open Source Link Protocol and Controller☆27Updated 4 years ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- SKY130 ReRAM and examples (SkyWater Provided)☆42Updated 3 years ago
- BAG (BAG AMS Generator) Primitives Library for SKY130☆19Updated 2 years ago
- A configurable general purpose graphics processing unit for☆11Updated 6 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Library of example SystemC/TLM peripherals for various SoCs based on the SCS library☆14Updated last week
- ☆17Updated last year
- ☆27Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated this week
- SRAM macros created for the GF180MCU provided by GlobalFoundries.☆18Updated 2 years ago
- LibreSilicon's Standard Cell Library Generator☆21Updated last month
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- Wraps the NVDLA project for Chipyard integration☆22Updated 3 months ago
- HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.☆34Updated last week
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆34Updated 6 months ago
- ☆14Updated 5 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated 9 months ago
- 7 track standard cells for GF180MCU provided by GlobalFoundries.☆27Updated 3 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- Verilog RTL Implementation of DNN☆10Updated 7 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Updated 2 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆18Updated 7 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 3 years ago
- A DMA Controller for RISCV CPUs☆13Updated 10 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago