google / chiplets-cost-modelLinks
☆24Updated 3 years ago
Alternatives and similar repositories for chiplets-cost-model
Users that are interested in chiplets-cost-model are comparing it to the libraries listed below
Sorting:
- SRAM build space for SKY130 provided by SkyWater.☆24Updated 4 years ago
- A configurable general purpose graphics processing unit for☆11Updated 6 years ago
- ☆27Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆27Updated last year
- Verilog RTL Implementation of DNN☆10Updated 7 years ago
- Integration test for entire CGRA flow☆12Updated 5 years ago
- SmartNIC☆14Updated 7 years ago
- SKY130 ReRAM and examples (SkyWater Provided)☆42Updated 3 years ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Updated 3 years ago
- "High density" digital standard cells for SKY130 provided by SkyWater.☆18Updated 2 years ago
- ☆29Updated 8 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- 7 track standard cells for GF180MCU provided by GlobalFoundries.☆27Updated 3 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 6 months ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Updated 5 years ago
- CNN accelerator☆27Updated 8 years ago
- Benchmarks for High-Level Synthesis☆10Updated 2 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- ☆20Updated last year
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Updated 6 years ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆22Updated last year
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated last week
- SCARV: a side-channel hardened RISC-V platform☆28Updated 2 years ago