Alternatives and similar repositories for chiplets-cost-model

Users that are interested in chiplets-cost-model are comparing it to the libraries listed below

• google / skywater-pdk-libs-sky130_fd_bd_sram
  SRAM build space for SKY130 provided by SkyWater.
  ☆22Updated 3 years ago
• google / globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
  7 track standard cells for GF180MCU provided by GlobalFoundries.
  ☆27Updated 2 years ago
• google / globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
  9 track standard cells for GF180MCU provided by GlobalFoundries.
  ☆18Updated 2 years ago
• google / skywater-pdk-libs-sky130_fd_pr_reram
  SKY130 ReRAM and examples (SkyWater Provided)
  ☆41Updated 3 years ago
• google / open-chiplet
  ☆27Updated 4 years ago
• google / globalfoundries-pdks
  Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.
  ☆48Updated 3 years ago
• google / skywater-pdk-libs-sky130_bag3_pr
  BAG (BAG AMS Generator) Primitives Library for SKY130
  ☆18Updated 2 years ago
• google / verilogpp
  ☆17Updated last year
• SLink-Protocol / S-Link
  An Open Source Link Protocol and Controller
  ☆27Updated 4 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• google / globalfoundries-pdk-ip-gf180mcu_fd_ip_sram
  SRAM macros created for the GF180MCU provided by GlobalFoundries.
  ☆17Updated 2 years ago
• gjlies / configgpgpu
  A configurable general purpose graphics processing unit for
  ☆11Updated 6 years ago
• google / globalfoundries-pdk-libs-gf180mcu_fd_pr
  Primitives for GF180MCU provided by GlobalFoundries.
  ☆53Updated 2 years ago
• google / skywater-pdk-libs-sky130_fd_sc_hd
  "High density" digital standard cells for SKY130 provided by SkyWater.
  ☆17Updated 2 years ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆43Updated 4 months ago
• cornell-brg / pyhdl-eval
  LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs
  ☆17Updated last year
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆42Updated this week
• StanfordAHA / CGRAFlow
  Integration test for entire CGRA flow
  ☆12Updated 5 years ago
• opencomputeproject / ODSA-BoW
  Repo for all activity related to the ODSA Bunch of Wires Specification
  ☆26Updated last year
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 3 months ago
• ucb-bar / nvdla-wrapper
  Wraps the NVDLA project for Chipyard integration
  ☆21Updated last month
• OSU-STARLAB / GPGPU-Ramulator-Simulator
  Replace original DRAM model in GPGPU-sim with Ramulator DRAM model
  ☆19Updated 6 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆22Updated 2 weeks ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆21Updated 3 years ago
• hyf6661669 / ARM_documents
  Documents for ARM
  ☆26Updated 5 months ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆54Updated this week
• gilani / fpfma
  Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)
  ☆22Updated 12 years ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆20Updated last week
• wallento / riscv-python-model
  Python Model of the RISC-V ISA
  ☆56Updated 3 years ago