AIB Generator: Analog hardware compiler for AIB PHY
☆40Aug 22, 2020Updated 5 years ago
Alternatives and similar repositories for aib-phy-generator
Users that are interested in aib-phy-generator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Home of the Advanced Interface Bus (AIB) specification.☆62Aug 30, 2022Updated 3 years ago
- ☆32Feb 20, 2024Updated 2 years ago
- ☆69Jan 7, 2023Updated 3 years ago
- Berkeley Analog Generator☆16Apr 3, 2019Updated 7 years ago
- BAG framework☆44Jul 24, 2024Updated 2 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- BAG (BAG AMS Generator) Primitives Library for SKY130☆22May 16, 2023Updated 3 years ago
- Hdl21 Schematics☆17Jan 24, 2024Updated 2 years ago
- genetic and neural net optimization for circuit design☆19Mar 29, 2022Updated 4 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆30Jan 25, 2024Updated 2 years ago
- Analog Placement Quality Prediction☆26Mar 24, 2023Updated 3 years ago
- BAG2 workspace for fake PDK (cds_ff_mpt)☆61May 20, 2020Updated 6 years ago
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆27Mar 11, 2023Updated 3 years ago
- ☆20Mar 29, 2022Updated 4 years ago
- ☆172Dec 4, 2022Updated 3 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- 12 bit SAR ADC IP in Skywater 130 nm PDK☆32May 30, 2024Updated 2 years ago
- Raw data collected about the SKY130 process technology.☆64May 7, 2023Updated 3 years ago
- Governance-related CHIPS Alliance documents, guides etc.☆10Feb 20, 2023Updated 3 years ago
- EE P 520 A Wi 20: Software Engineering For Embedded Applications☆11Mar 13, 2020Updated 6 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆45Apr 13, 2023Updated 3 years ago
- ☆31Feb 4, 2021Updated 5 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆15Jul 22, 2020Updated 6 years ago
- A universal Sentaurus Workbench automated simulation and parameter optimization tool that combines DeepSeek AI and swbpy2, supporting Sen…☆23Apr 22, 2025Updated last year
- Python framework for the reverse engineering of Hamiltonian models of quantum systems through machine learning.☆22Mar 31, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆23May 21, 2023Updated 3 years ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆17Updated this week
- Design of BandGapReference Circuit using Sky130 PDK☆11Oct 30, 2021Updated 4 years ago
- NumBAT, the Numerical Brillouin Analysis Tool, integrates electromagnetic and acoustic mode solvers to calculate the interactions of opti…☆18Jan 3, 2023Updated 3 years ago
- An open source generator for standard cell based memories.☆14Sep 6, 2016Updated 9 years ago
- ☆13Jul 5, 2026Updated last month
- Python binding for KLU solver☆11Apr 6, 2016Updated 10 years ago
- Interchange formats for chip design.☆39Feb 15, 2026Updated 5 months ago
- This repository contains my work from the VLSI System Design (VSD) Workshop on 7nm FinFET Circuit Design and Characterization using the A…☆16Sep 9, 2025Updated 11 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- fakeram generator for use by researchers who do not have access to commercial ram generators☆43Jan 13, 2023Updated 3 years ago
- Automatic generation of real number models from analog circuits☆49Apr 2, 2024Updated 2 years ago
- Cell layout generation (MH Multiheight) for DTCO/STCO exploration toolkit.☆15Oct 6, 2025Updated 10 months ago
- A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement,…☆16Mar 8, 2026Updated 5 months ago
- Documentation for the entire CGRAFlow☆19Sep 17, 2021Updated 4 years ago
- Image classification on lung and colon cancer histopathological images through Capsule Networks or CapsNets.☆12Jan 7, 2021Updated 5 years ago
- This repository contains MATLAB code which can be used to generate simulink model and HDL code for implementation on FPGA. Since HDL code…☆14May 6, 2020Updated 6 years ago