spcl / rapidchiplet
A toolchain for rapid design space exploration of chiplet architectures
☆44Updated last week
Alternatives and similar repositories for rapidchiplet:
Users that are interested in rapidchiplet are comparing it to the libraries listed below
- A list of our chiplet simulaters☆31Updated 3 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆62Updated 8 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆70Updated 3 years ago
- An Open-Source Tool for CGRA Accelerators☆59Updated 2 months ago
- ☆29Updated 3 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- The open-sourced version of BOOM-Explorer☆38Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…☆33Updated last week
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆69Updated 5 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆45Updated this week
- cycle accurate Network-on-Chip Simulator☆27Updated last year
- ☆42Updated last week
- ☆25Updated 4 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆89Updated 5 months ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated last year
- ☆57Updated last year
- A High-Level DRAM Timing, Power and Area Exploration Tool☆28Updated 4 years ago
- An integrated CGRA design framework☆87Updated last week
- CATCH 1.0, Initial full release of CATCH cost model.☆11Updated last month
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆64Updated this week
- Project repo for the POSH on-chip network generator☆44Updated last week
- CGRA framework with vectorization support.☆28Updated this week
- ☆12Updated 3 months ago
- ☆25Updated last year
- An infrastructure for integrated EDA☆38Updated last year
- Dataset for ML-guided Accelerator Design☆36Updated 4 months ago
- ☆35Updated 3 years ago