Alternatives and similar repositories for rapidchiplet:

Users that are interested in rapidchiplet are comparing it to the libraries listed below

• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆28Updated 3 years ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆62Updated 7 months ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆58Updated last month
• mec-UMN / HISIM
  HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…
  ☆30Updated 2 months ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆34Updated 3 months ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆85Updated 3 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆68Updated 3 years ago
• pnnl / soda-opt
  ☆40Updated last week
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆48Updated 7 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆84Updated 4 months ago
• baichen318 / boom-explorer-public
  The open-sourced version of BOOM-Explorer
  ☆36Updated last year
• Yinxiao-Feng / chiplet-network-sim
  ☆23Updated 2 months ago
• CMU-SAFARI / VAMPIRE
  An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …
  ☆38Updated 5 years ago
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆14Updated 2 years ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆59Updated 2 months ago
• esl-epfl / HEEPsilon
  A low power platform based on X-HEEP and integrating the ESL-CGRA
  ☆13Updated 4 months ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆24Updated 3 years ago
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆23Updated last year
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆43Updated last year
• tukl-msd / DRAMSpec
  A High-Level DRAM Timing, Power and Area Exploration Tool
  ☆27Updated 4 years ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆118Updated 2 weeks ago
• ecolab-nus / morpher-v2
  An Open-Source Tool for CGRA Accelerators
  ☆18Updated 9 months ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆25Updated this week
• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆67Updated 5 years ago
• VeriGOOD-ML / public
  ☆53Updated last year
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆57Updated 4 months ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆79Updated 6 years ago
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆22Updated last year
• hkust-zhiyao / PANDA
  PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
  ☆14Updated last year
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆61Updated 3 years ago