opencomputeproject / ODSA-BoWLinks
Repo for all activity related to the ODSA Bunch of Wires Specification
☆26Updated last year
Alternatives and similar repositories for ODSA-BoW
Users that are interested in ODSA-BoW are comparing it to the libraries listed below
Sorting:
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆71Updated last year
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- ☆28Updated 7 years ago
- ☆67Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Next generation CGRA generator☆113Updated this week
- Project repo for the POSH on-chip network generator☆50Updated 5 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- SoCRocket - Core Repository☆38Updated 8 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 3 months ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- ☆15Updated 4 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆37Updated 3 months ago
- ☆41Updated 7 years ago
- For contributions of Chisel IP to the chisel community.☆65Updated 9 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 weeks ago
- Public release☆57Updated 6 years ago
- DASS HLS Compiler☆29Updated last year
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago
- ☆44Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- LIS Network-on-Chip Implementation☆31Updated 9 years ago