Repo for all activity related to the ODSA Bunch of Wires Specification
☆30Jan 25, 2024Updated 2 years ago
Alternatives and similar repositories for ODSA-BoW
Users that are interested in ODSA-BoW are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Wavious Wlink☆12Oct 28, 2021Updated 4 years ago
- ☆25Aug 9, 2022Updated 3 years ago
- Home of the Advanced Interface Bus (AIB) specification.☆58Aug 30, 2022Updated 3 years ago
- OpenROAD Agent. This repository contain the model to train and testing the model using EDA Corpus dataset.☆22Jul 24, 2025Updated 7 months ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- Switches for HIRE: Resource Scheduling for Data Center In-Network Computing☆13Jan 18, 2021Updated 5 years ago
- SmartNIC☆14Dec 13, 2018Updated 7 years ago
- 生态模拟仿真系统☆10Aug 5, 2020Updated 5 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆148Sep 23, 2024Updated last year
- AIB Generator: Analog hardware compiler for AIB PHY☆39Aug 22, 2020Updated 5 years ago
- Enhanced PQOS (Intel RDT Software) with DDIO-related Functionalities☆16May 25, 2022Updated 3 years ago
- Chisel Fixed-Point Arithmetic Library☆18Dec 15, 2025Updated 3 months ago
- ☆48Dec 20, 2025Updated 3 months ago
- RSSI-based OFDM signal classification using a machine learning algorithm.☆12May 15, 2018Updated 7 years ago
- ☆14Mar 13, 2026Updated last week
- tool for converting vcd(value change dump) to ate pattern.☆11Oct 22, 2015Updated 10 years ago
- A collection of examples showcasing PyCDE and Mini RISC-V implementation.☆10Dec 14, 2025Updated 3 months ago
- A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement,…☆15Mar 8, 2026Updated 2 weeks ago
- Tool for converting PyTorch models into raw C codes with minimal dependency and some performance optimizations.☆45Sep 1, 2025Updated 6 months ago
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development☆16Nov 7, 2022Updated 3 years ago
- RTL code of some arbitration algorithm☆16Aug 25, 2019Updated 6 years ago
- Hardened RISC-V core☆15Mar 12, 2026Updated last week
- RTLCheck☆25Oct 9, 2018Updated 7 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆124Jul 22, 2021Updated 4 years ago
- MIAOW2.0 FPGA implementable design☆12Oct 18, 2017Updated 8 years ago
- ☆17Mar 6, 2026Updated 2 weeks ago
- Multi-platform topology-aware memory management library☆13Apr 23, 2020Updated 5 years ago
- FeRTOS is a simple "operating system" that currently supports ARM Cortex-M CPUs☆13Jul 9, 2022Updated 3 years ago
- This is the matlab code of deep convolutional neural networks (CNNs) for modulation classification of OFDM burst signals☆14Jun 3, 2021Updated 4 years ago
- WiPhy is an open-source Python package for wireless signal processing at the physical layer.☆16Jul 16, 2025Updated 8 months ago
- ☆27Aug 2, 2021Updated 4 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated 10 months ago
- ☆22Oct 24, 2020Updated 5 years ago
- The multi-core cluster of a PULP system.☆113Mar 12, 2026Updated last week
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆91Jul 29, 2019Updated 6 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Apr 13, 2023Updated 2 years ago
- Demo SoC for SiliconCompiler.☆62Mar 2, 2026Updated 3 weeks ago
- Tools to enumerate and find Bluetooth Adapters☆14Mar 16, 2026Updated last week