opencomputeproject / ODSA-BoWLinks
Repo for all activity related to the ODSA Bunch of Wires Specification
☆24Updated last year
Alternatives and similar repositories for ODSA-BoW
Users that are interested in ODSA-BoW are comparing it to the libraries listed below
Sorting:
- ☆15Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆105Updated last year
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆33Updated 2 weeks ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆36Updated 3 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆40Updated 2 weeks ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated 3 weeks ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 2 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- A Rocket-based RISC-V superscalar in-order core☆33Updated last month
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- Project repo for the POSH on-chip network generator☆46Updated 2 months ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 weeks ago
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated 3 weeks ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆27Updated 5 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- ☆44Updated 5 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- Next generation CGRA generator☆111Updated this week
- sram/rram/mram.. compiler☆35Updated last year
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- ☆61Updated this week
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆68Updated 9 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago