intel / aib-phy-hardwareLinks
☆67Updated 2 years ago
Alternatives and similar repositories for aib-phy-hardware
Users that are interested in aib-phy-hardware are comparing it to the libraries listed below
Sorting:
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Updated 2 years ago
- ideas and eda software for vlsi design☆51Updated 2 weeks ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- Next generation CGRA generator☆118Updated last week
- Project repo for the POSH on-chip network generator☆52Updated 9 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- Builds, flow and designs for the alpha release☆54Updated 6 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆66Updated 3 years ago
- ☆44Updated 5 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated last month
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆120Updated 4 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆144Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 2 months ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆49Updated 4 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated last year
- This is a tutorial on standard digital design flow☆80Updated 4 years ago
- Verilog Content Addressable Memory Module☆113Updated 3 years ago
- Open Source PHY v2☆31Updated last year
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- Ethernet interface modules for Cocotb☆72Updated 3 months ago
- ☆57Updated 2 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- Public release☆58Updated 6 years ago