An open-source UCIe implementation
☆125Aug 28, 2026Updated this week
Alternatives and similar repositories for ucie
Users that are interested in ucie are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An open-source UCIe implementation developed at UC Berkeley.☆20Jul 8, 2024Updated 2 years ago
- A Heterogeneous GPU Platform for AI and Neural Graphics☆67Aug 13, 2026Updated 2 weeks ago
- Complete UCIe v2.0 Controller RTL Implementation with Revolutionary 128 Gbps PAM4 Signaling - Architecture Design Complete, Ready for RTL…☆37Aug 30, 2025Updated last year
- Universal Memory Interface (UMI)☆162Updated this week
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆62Jan 20, 2026Updated 7 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Advanced Interface Bus (AIB) die-to-die hardware open source☆149Sep 23, 2024Updated last year
- A configurable SRAM generator☆69Aug 19, 2026Updated last week
- A Chisel RTL generator for network-on-chip interconnects☆233Nov 7, 2025Updated 9 months ago
- gem5 repository to study chiplet-based systems☆91Apr 18, 2019Updated 7 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,370Aug 19, 2026Updated last week
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆21Apr 28, 2026Updated 4 months ago
- PAST SHORT COURSES AND TUTORIALS FROM ISSCC.☆17Apr 7, 2024Updated 2 years ago
- HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…☆65Mar 29, 2026Updated 5 months ago
- A verilog implementation for Network-on-Chip☆87Feb 3, 2018Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The 'missing header' for Chisel☆24Feb 5, 2026Updated 6 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆113Aug 19, 2026Updated last week
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆56Updated this week
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆40Nov 24, 2022Updated 3 years ago
- ☆92Aug 14, 2026Updated 2 weeks ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated 2 years ago
- ☆246Jun 25, 2025Updated last year
- ☆13Oct 11, 2024Updated last year
- ☆32Feb 20, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The official repository for the gem5 computer-system architecture simulator.☆15Updated this week
- RTL for AXI over UCIe bridge.☆28Aug 17, 2026Updated last week
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆69Aug 18, 2026Updated last week
- Chisel RISC-V Vector 1.0 Implementation☆157Updated this week
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆14Jan 4, 2021Updated 5 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Jan 6, 2023Updated 3 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆31Jan 25, 2024Updated 2 years ago
- A Fast, Low-Overhead On-chip Network☆336Aug 14, 2026Updated 2 weeks ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆940Aug 18, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆18Mar 11, 2026Updated 5 months ago
- ☆17Updated this week
- ☆20Mar 18, 2022Updated 4 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆26Jul 12, 2023Updated 3 years ago
- A machine learning accelerator core designed for energy-efficient AI at the edge.☆2,533Updated this week
- ☆15Dec 9, 2025Updated 8 months ago
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆506Aug 3, 2024Updated 2 years ago