An open-source UCIe implementation
☆122Jul 14, 2026Updated last week
Alternatives and similar repositories for ucie
Users that are interested in ucie are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An open-source UCIe implementation developed at UC Berkeley.☆20Jul 8, 2024Updated 2 years ago
- A Heterogeneous GPU Platform for AI and Neural Graphics☆61Jun 22, 2026Updated 3 weeks ago
- Complete UCIe v2.0 Controller RTL Implementation with Revolutionary 128 Gbps PAM4 Signaling - Architecture Design Complete, Ready for RTL…☆34Aug 30, 2025Updated 10 months ago
- Universal Memory Interface (UMI)☆162Updated this week
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆55Jan 20, 2026Updated 6 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Advanced Interface Bus (AIB) die-to-die hardware open source☆149Sep 23, 2024Updated last year
- A Chisel RTL generator for network-on-chip interconnects☆233Nov 7, 2025Updated 8 months ago
- gem5 repository to study chiplet-based systems☆90Apr 18, 2019Updated 7 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,335Updated this week
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Jan 6, 2023Updated 3 years ago
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆21Apr 28, 2026Updated 2 months ago
- PAST SHORT COURSES AND TUTORIALS FROM ISSCC.☆17Apr 7, 2024Updated 2 years ago
- ☆15Dec 9, 2025Updated 7 months ago
- HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…☆65Mar 29, 2026Updated 3 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A verilog implementation for Network-on-Chip☆85Feb 3, 2018Updated 8 years ago
- The 'missing header' for Chisel☆24Feb 5, 2026Updated 5 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆110May 22, 2026Updated last month
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆40Nov 24, 2022Updated 3 years ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated 2 years ago
- ☆241Jun 25, 2025Updated last year
- ☆13Oct 11, 2024Updated last year
- RTL for AXI over UCIe bridge.☆21Updated this week
- ☆32Feb 20, 2024Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- The official repository for the gem5 computer-system architecture simulator.☆15May 12, 2026Updated 2 months ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆69Updated this week
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆293Mar 26, 2022Updated 4 years ago
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆14Jan 4, 2021Updated 5 years ago
- Parametric AXI4 crossbar in SystemVerilog☆237May 25, 2026Updated last month
- Repo for all activity related to the ODSA Bunch of Wires Specification☆30Jan 25, 2024Updated 2 years ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆931Jul 8, 2026Updated last week
- A Fast, Low-Overhead On-chip Network☆319Updated this week
- ☆18Mar 11, 2026Updated 4 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆17Updated this week
- ☆20Mar 18, 2022Updated 4 years ago
- A machine learning accelerator core designed for energy-efficient AI at the edge.☆2,467Updated this week
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆25Jul 12, 2023Updated 3 years ago
- Chisel RISC-V Vector 1.0 Implementation☆153Jul 14, 2026Updated last week
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆492Aug 3, 2024Updated last year
- A configurable SRAM generator☆66Jun 28, 2026Updated 3 weeks ago