chipsalliance / AIB-specificationLinks
Home of the Advanced Interface Bus (AIB) specification.
☆58Updated 3 years ago
Alternatives and similar repositories for AIB-specification
Users that are interested in AIB-specification are comparing it to the libraries listed below
Sorting:
- Advanced Interface Bus (AIB) die-to-die hardware open source☆146Updated last year
- ☆113Updated 2 months ago
- A dynamic verification library for Chisel.☆160Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆122Updated 4 years ago
- A Fast, Low-Overhead On-chip Network☆265Updated this week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆309Updated 3 months ago
- ☆68Updated 3 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆148Updated 3 weeks ago
- A complete open-source design-for-testing (DFT) Solution☆178Updated 5 months ago
- Python packages providing a library for Verification Stimulus and Coverage☆137Updated 2 weeks ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆28Updated 4 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆200Updated 5 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆186Updated last year
- Network on Chip Implementation written in SytemVerilog☆197Updated 3 years ago
- ☆187Updated 4 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆163Updated 2 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆280Updated last month
- An Open-Source Design and Verification Environment for RISC-V☆86Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated last month
- AMC: Asynchronous Memory Compiler☆52Updated 5 years ago
- ☆232Updated 10 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 3 years ago
- An open source generator for standard cell based memories.☆14Updated 9 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- ☆101Updated 5 months ago
- This is a tutorial on standard digital design flow☆83Updated 4 years ago