chipsalliance / AIB-specificationLinks
Home of the Advanced Interface Bus (AIB) specification.
☆52Updated 2 years ago
Alternatives and similar repositories for AIB-specification
Users that are interested in AIB-specification are comparing it to the libraries listed below
Sorting:
- ☆96Updated last year
- ☆66Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆138Updated 9 months ago
- AIB Generator: Analog hardware compiler for AIB PHY☆34Updated 4 years ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last year
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆60Updated 4 years ago
- Verilator open-source SystemVerilog simulator and lint system☆39Updated 3 weeks ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 8 months ago
- SystemVerilog modules and classes commonly used for verification☆48Updated 5 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- Project repo for the POSH on-chip network generator☆46Updated 3 months ago
- Logic synthesis and ABC based optimization☆49Updated 2 weeks ago
- Next generation CGRA generator☆112Updated this week
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 7 months ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- Announcements related to Verilator☆39Updated 5 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆136Updated last week
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 4 months ago
- For contributions of Chisel IP to the chisel community.☆62Updated 7 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 3 months ago
- Python wrapper for verilator model☆86Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago