Alternatives and similar repositories for AIB-specification:

Users that are interested in AIB-specification are comparing it to the libraries listed below

• chipsalliance / uvm-verilator
  ☆92Updated last year
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆48Updated 4 years ago
• intel / aib-phy-hardware
  ☆66Updated 2 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆102Updated 3 years ago
• chipsalliance / aib-phy-generator
  AIB Generator: Analog hardware compiler for AIB PHY
  ☆33Updated 4 years ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆134Updated 6 months ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆35Updated 2 years ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆27Updated 4 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 11 months ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 4 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆49Updated this week
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆57Updated 3 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆47Updated 3 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆133Updated 3 weeks ago
• chipsalliance / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆38Updated this week
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆83Updated 4 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 5 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆62Updated 7 months ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆61Updated last year
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆90Updated 5 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆189Updated last week
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆52Updated 11 months ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆59Updated 4 years ago
• The-OpenROAD-Project / yosys
  Logic synthesis and ABC based optimization
  ☆49Updated last week
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆80Updated last year
• bsg-idea / uw_openroad_free45
  UW reference flow for Free45PDK and The OpenROAD Project
  ☆11Updated 4 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆273Updated this week
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆60Updated last week
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆75Updated 3 years ago