PacoReinaCampo / SoC-RISCVLinks
System on Chip with RISCV-32 / RISCV-64 / RISCV-128
☆22Updated last month
Alternatives and similar repositories for SoC-RISCV
Users that are interested in SoC-RISCV are comparing it to the libraries listed below
Sorting:
- An Open Source Link Protocol and Controller☆27Updated 4 years ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- Synchronous FIFOs designed in Verilog/System Verilog.☆24Updated last month
- Advanced Debug Interface☆14Updated 10 months ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 9 months ago
- ASIC Design of the openSPARC Floating Point Unit☆15Updated 8 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Updated 5 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Updated last month
- A configurable general purpose graphics processing unit for☆11Updated 6 years ago
- ☆18Updated 5 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Theia: ray graphic processing unit☆20Updated 11 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 8 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated this week
- Hardware Description Language Translator☆17Updated this week
- Ethernet MAC 10/100 Mbps☆28Updated 4 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Generic AXI master stub☆19Updated 11 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 10 months ago
- Open FPGA Modules☆24Updated last year
- Xilinx Unisim Library in Verilog☆87Updated 5 years ago
- ☆13Updated 4 years ago
- Network on Chip for MPSoC☆28Updated last month
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆22Updated 2 years ago
- SystemC to Verilog Synthesizable Subset Translator☆12Updated 2 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated 2 years ago