VeriGOOD-ML / public
☆47Updated 8 months ago
Related projects: ⓘ
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆60Updated 2 years ago
- ☆65Updated last year
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆26Updated last year
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆23Updated 4 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆19Updated last month
- ☆31Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆77Updated last month
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆31Updated 4 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- A DSL for Systolic Arrays☆73Updated 5 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆48Updated 2 years ago
- HLS for Networks-on-Chip☆27Updated 3 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆58Updated 9 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆62Updated last month
- Dataset for ML-guided Accelerator Design☆30Updated 5 months ago
- CGRA framework with vectorization support.☆18Updated 5 months ago
- ☆33Updated 6 months ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆25Updated last week
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆34Updated this week
- Processing in Memory Emulation☆18Updated last year
- ☆20Updated last year
- ☆27Updated 5 years ago
- ACM TODAES Best Paper Award, 2022☆23Updated 10 months ago
- ☆21Updated 4 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆28Updated 4 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆25Updated last month
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆62Updated 5 years ago
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆18Updated 9 months ago