alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-CoresLinks
☆31Updated 2 months ago
Alternatives and similar repositories for Mixed-precision-Neural-Networks-on-RISC-V-Cores
Users that are interested in Mixed-precision-Neural-Networks-on-RISC-V-Cores are comparing it to the libraries listed below
Sorting:
- ☆17Updated 2 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆57Updated last month
- eyeriss-chisel3☆41Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆30Updated 10 months ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- RTL implementation of Flex-DPE.☆107Updated 5 years ago
- ☆47Updated 3 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆56Updated 4 months ago
- vector accelerating unit☆29Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 10 months ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆58Updated 3 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆30Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- ☆72Updated 2 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated last year
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- ☆34Updated 6 years ago
- An integrated CGRA design framework☆90Updated 4 months ago
- Hardware accelerator for convolutional neural networks☆47Updated 2 years ago
- RTL generator for SpGEMM☆12Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆94Updated 10 months ago
- An Open-Source Tool for CGRA Accelerators☆67Updated 3 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆60Updated 4 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago