Alternatives and similar repositories for Mixed-precision-Neural-Networks-on-RISC-V-Cores

Users that are interested in Mixed-precision-Neural-Networks-on-RISC-V-Cores are comparing it to the libraries listed below

• gem5-X / TiC-SAT
  ☆16Updated 3 weeks ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆53Updated last month
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆77Updated 3 years ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 4 years ago
• kuladeepsaireddy / OpenNoc
  ☆33Updated 6 years ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆53Updated 2 months ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆39Updated 2 years ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆43Updated 8 months ago
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆27Updated last year
• iitm-sysdl / FuSeConv
  Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021
  ☆14Updated 3 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆30Updated 4 years ago
• alibaba / vector-accelerating-unit
  vector accelerating unit
  ☆29Updated 4 years ago
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated last year
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆27Updated 3 years ago
• sfu-arch / SPAGHETTI
  RTL generator for SpGEMM
  ☆12Updated 4 years ago
• fffasttime / AnyPackingNet
  ☆27Updated 2 months ago
• pulp-platform / ITA
  ☆47Updated last month
• hngenc / stellar
  ☆29Updated 6 months ago
• wubinyi / Convolutional-Neural-Network-Accelerator
  Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).
  ☆21Updated 6 years ago
• kelvin0207 / SparSynergy
  Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…
  ☆16Updated 2 months ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆26Updated 4 years ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆65Updated last month
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆100Updated 5 years ago
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆24Updated 2 years ago
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆24Updated last year
• SuperLiaoXH / SystolicArray-2D-FP16
  基于FP16的二维脉动阵列电路设计
  ☆11Updated 2 years ago