Alternatives and similar repositories for Mixed-precision-Neural-Networks-on-RISC-V-Cores

Users that are interested in Mixed-precision-Neural-Networks-on-RISC-V-Cores are comparing it to the libraries listed below

• gem5-X / TiC-SAT
  ☆19Updated 7 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆83Updated 4 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆64Updated 5 months ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆38Updated 4 years ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆73Updated last month
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆75Updated 3 weeks ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 4 years ago
• VCA-EPFL / FSA
  FSA: Fusing FlashAttention within a Single Systolic Array
  ☆77Updated 4 months ago
• pulp-platform / ITA
  ☆60Updated 8 months ago
• alibaba / vector-accelerating-unit
  vector accelerating unit
  ☆35Updated 5 years ago
• hyoukjun / microswitch-noc
  ☆28Updated 6 years ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆21Updated 4 years ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆29Updated 4 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆92Updated last year
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆49Updated 9 months ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆21Updated 3 years ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆115Updated 5 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆30Updated 6 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 9 months ago
• pulp-platform / fpu
  ☆57Updated 6 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆25Updated 4 years ago
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆67Updated 2 weeks ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆69Updated 2 months ago
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆38Updated 5 months ago
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆35Updated 2 years ago
• hngenc / stellar
  ☆32Updated last year
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆60Updated 4 years ago