☆38Oct 21, 2025Updated 5 months ago
Alternatives and similar repositories for Mixed-precision-Neural-Networks-on-RISC-V-Cores
Users that are interested in Mixed-precision-Neural-Networks-on-RISC-V-Cores are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆25May 26, 2022Updated 3 years ago
- PyTorchSim is a Comprehensive, Fast, and Accurate NPU Simulation Framework☆100Updated this week
- Tender: Accelerating Large Language Models via Tensor Decompostion and Runtime Requantization (ISCA'24)☆31Jul 4, 2024Updated last year
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 7 years ago
- Optimizing the Deployment of Tiny Transformers on Low-Power MCUs☆33Sep 2, 2024Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆22Mar 29, 2025Updated 11 months ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends☆33Updated this week
- ☆29Oct 20, 2019Updated 6 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆22Apr 25, 2025Updated 11 months ago
- A Custom RISC-V Instruction Extension for SNN and CNN Computation☆34Aug 22, 2024Updated last year
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆93Jan 5, 2025Updated last year
- Dual-Core Out-of-Order MIPS CPU Design☆21May 8, 2025Updated 10 months ago
- ☆25Mar 1, 2023Updated 3 years ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- Reconfigurable Binary Engine☆17Mar 23, 2021Updated 5 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- An almost empty chisel project as a starting point for hardware design☆35Jan 27, 2025Updated last year
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- ☆13Jul 28, 2022Updated 3 years ago
- Exploring how optimizations for GEMMs work☆29Feb 28, 2026Updated 3 weeks ago
- Hack@DAC 2021☆18Jul 24, 2024Updated last year
- [CVPR 2025 Highlight] FIMA-Q: Post-Training Quantization for Vision Transformers by Fisher Information Matrix Approximation☆25Jun 16, 2025Updated 9 months ago
- Cavs: An Efficient Runtime System for Dynamic Neural Networks☆15Sep 18, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Input / Output Physical Memory Protection Unit for RISC-V☆15Jul 20, 2023Updated 2 years ago
- Load and run Llama from safetensors files in C☆15Oct 24, 2024Updated last year
- Accelerate multihead attention transformer model using HLS for FPGA☆11Dec 7, 2023Updated 2 years ago
- ☆68Apr 22, 2025Updated 11 months ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- ☆10Dec 15, 2023Updated 2 years ago
- ☆21Sep 26, 2025Updated 6 months ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- ☆23Mar 12, 2026Updated 2 weeks ago
- NordVPN Threat Protection Pro™ • AdTake your cybersecurity to the next level. Block phishing, malware, trackers, and ads. Lightweight app that works with all browsers.
- ☆18Feb 3, 2022Updated 4 years ago
- ☆118Nov 17, 2023Updated 2 years ago
- Course Project for High Level Chip Design （高层次芯片设计）☆17Jan 2, 2025Updated last year
- ☆20May 13, 2025Updated 10 months ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 3 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Updated this week