taichi-ishitani / riceLinks
☆14Updated 2 weeks ago
Alternatives and similar repositories for rice
Users that are interested in rice are comparing it to the libraries listed below
Sorting:
- ☆30Updated last week
- Basic Common Modules☆41Updated 2 months ago
- YosysHQ SVA AXI Properties☆41Updated 2 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated 2 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated this week
- ☆17Updated last week
- Design and UVM-TB of RISC -V Microprocessor☆23Updated last year
- SystemVerilog Linter based on pyslang☆31Updated 2 months ago
- ☆14Updated 4 months ago
- ☆20Updated 5 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆19Updated 3 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆11Updated 2 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆34Updated 7 months ago
- CORE-V MCU UVM Environment and Test Bench☆21Updated last year
- A simple, scalable, source-synchronous, all-digital DDR link☆28Updated last month
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- UVM components for DSP tasks (MODulation/DEModulation)☆14Updated 3 years ago
- LIS Network-on-Chip Implementation☆31Updated 8 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆30Updated 2 months ago
- ☆10Updated last year
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Updated 2 months ago
- ☆27Updated this week
- The memory model was leveraged from micron.☆22Updated 7 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- APB Logic☆19Updated 7 months ago
- SystemVerilog FSM generator☆32Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago